diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-14 22:12:12 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-10-16 04:03:08 +0000 |
| commit | 3f561a8e081f1256dcd6be1a0f4107b114a14ea1 (patch) | |
| tree | 30fb6868ff6f146381a9f6f1a6bdf4b33ae279cc /src | |
| parent | 6147314344ae257081ec91dd709b18da283878fc (diff) | |
mb/intel/adlrvp: Enable Hybrid storage mode
TEST=Build and test booting ADL RVP form NVMe and Optane
localhost ~ # lspci -d :f1a6
Show all the NVMe devices and be really verbose
localhost ~ # lspci -vvvd :f1a6
Print PCIe lane capabilities and configurations for all the NVMe devices.
Change-Id: I0a04b23b17df574d4fa3bae233ca40cd3b104201
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index fadf602536..818f32f9fa 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -61,6 +61,8 @@ chip soc/intel/alderlake # Enable PCH PCIE RP 11 for optane register "PcieRpEnable[10]" = "1" + # Hybrid storage mode + register "HybridStorageMode" = "1" # Enable CPU PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40" |