soc/intel/tigerlake: Hook up FSP repository

Select `HAVE_INTEL_FSP_REPO` so that the FSP binary from the FSP
repository is used by default. Also, use the FSP headers from the FSP
repository and adjust some UPD names so that coreboot is able to use
them.

Also added new config FSP_TYPE_CLIENT/IOT. Respective mainboard Kconfigs
to select right FSP_TYPE when using FSP repository.

BUG=b:175957775
BRANCH=none

Change-Id: I5e694b91be7734dd98665051a6a3d9eccab7dac7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>

3 files changed, 52 insertions, 37 deletions

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index eb0fea9072..95a0337136 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -21,6 +21,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
 	select GENERIC_GPIO_LIB
 	select HAVE_FSP_GOP
+	select HAVE_INTEL_FSP_REPO
 	select INTEL_DESCRIPTOR_MODE_CAPABLE
 	select HAVE_SMI_HANDLER
 	select IDT_IN_EVERY_STAGE
@@ -212,11 +213,25 @@ config CBFS_SIZE
 	hex
 	default 0x200000
 
+config FSP_TYPE_IOT
+	bool
+	default n
+	help
+	  This option allows to select FSP IOT type from 3rdparty/fsp repo
+
+config FSP_TYPE_CLIENT
+	bool
+	default !FSP_TYPE_IOT
+	help
+	  This option allows to select FSP CLIENT type from 3rdparty/fsp repo
+
 config FSP_HEADER_PATH
-	default "src/vendorcode/intel/fsp/fsp2_0/tigerlake/"
+	default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Include/" if FSP_TYPE_IOT
+	default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Include/" if FSP_TYPE_CLIENT
 
 config FSP_FD_PATH
-	default "3rdparty/fsp/TigerLakeFspBinPkg/Fsp.fd"
+	default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Fsp.fd" if FSP_TYPE_IOT
+	default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Fsp.fd" if FSP_TYPE_CLIENT
 
 config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT
 	int "Debug Consent for TGL"
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 616daa08d1..220140bfd1 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -292,7 +292,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	 * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
 	 * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4
 	 */
-	params->LpmStateEnableMask = LPM_S0iX_ALL & ~get_disable_mask(config);
+	params->PmcLpmS0ixSubStateEnableMask = LPM_S0iX_ALL & ~get_disable_mask(config);
 
 	/*
 	 * Power Optimizer for DMI and SATA.
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c
index c030bb80ac..ce6316ed41 100644
--- a/src/soc/intel/tigerlake/meminit.c
+++ b/src/soc/intel/tigerlake/meminit.c
@@ -55,24 +55,24 @@ static const struct soc_mem_cfg soc_mem_cfg[] = {
 static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data)
 {
 	uint32_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = {
-		[0] = { &mem_cfg->MemorySpdPtr00, &mem_cfg->MemorySpdPtr01, },
-		[1] = { &mem_cfg->MemorySpdPtr02, &mem_cfg->MemorySpdPtr03, },
-		[2] = { &mem_cfg->MemorySpdPtr04, &mem_cfg->MemorySpdPtr05, },
-		[3] = { &mem_cfg->MemorySpdPtr06, &mem_cfg->MemorySpdPtr07, },
-		[4] = { &mem_cfg->MemorySpdPtr08, &mem_cfg->MemorySpdPtr09, },
-		[5] = { &mem_cfg->MemorySpdPtr10, &mem_cfg->MemorySpdPtr11, },
-		[6] = { &mem_cfg->MemorySpdPtr12, &mem_cfg->MemorySpdPtr13, },
-		[7] = { &mem_cfg->MemorySpdPtr14, &mem_cfg->MemorySpdPtr15, },
+		[0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, },
+		[1] = { &mem_cfg->MemorySpdPtr010, &mem_cfg->MemorySpdPtr011, },
+		[2] = { &mem_cfg->MemorySpdPtr020, &mem_cfg->MemorySpdPtr021, },
+		[3] = { &mem_cfg->MemorySpdPtr030, &mem_cfg->MemorySpdPtr031, },
+		[4] = { &mem_cfg->MemorySpdPtr100, &mem_cfg->MemorySpdPtr101, },
+		[5] = { &mem_cfg->MemorySpdPtr110, &mem_cfg->MemorySpdPtr111, },
+		[6] = { &mem_cfg->MemorySpdPtr120, &mem_cfg->MemorySpdPtr121, },
+		[7] = { &mem_cfg->MemorySpdPtr130, &mem_cfg->MemorySpdPtr131, },
 	};
 	uint8_t *disable_dimm_upds[MRC_CHANNELS] = {
-		&mem_cfg->DisableDimmCh0,
-		&mem_cfg->DisableDimmCh1,
-		&mem_cfg->DisableDimmCh2,
-		&mem_cfg->DisableDimmCh3,
-		&mem_cfg->DisableDimmCh4,
-		&mem_cfg->DisableDimmCh5,
-		&mem_cfg->DisableDimmCh6,
-		&mem_cfg->DisableDimmCh7,
+		&mem_cfg->DisableDimmMc0Ch0,
+		&mem_cfg->DisableDimmMc0Ch1,
+		&mem_cfg->DisableDimmMc0Ch2,
+		&mem_cfg->DisableDimmMc0Ch3,
+		&mem_cfg->DisableDimmMc1Ch0,
+		&mem_cfg->DisableDimmMc1Ch1,
+		&mem_cfg->DisableDimmMc1Ch2,
+		&mem_cfg->DisableDimmMc1Ch3,
 	};
 	int ch, dimm;
 
@@ -109,17 +109,17 @@ static void mem_init_dq_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_dat
 				const struct mb_cfg *mb_cfg)
 {
 	void *dq_upds[MRC_CHANNELS] = {
-		&mem_cfg->DqMapCpu2DramCh0,
-		&mem_cfg->DqMapCpu2DramCh1,
-		&mem_cfg->DqMapCpu2DramCh2,
-		&mem_cfg->DqMapCpu2DramCh3,
-		&mem_cfg->DqMapCpu2DramCh4,
-		&mem_cfg->DqMapCpu2DramCh5,
-		&mem_cfg->DqMapCpu2DramCh6,
-		&mem_cfg->DqMapCpu2DramCh7,
+		&mem_cfg->DqMapCpu2DramMc0Ch0,
+		&mem_cfg->DqMapCpu2DramMc0Ch1,
+		&mem_cfg->DqMapCpu2DramMc0Ch2,
+		&mem_cfg->DqMapCpu2DramMc0Ch3,
+		&mem_cfg->DqMapCpu2DramMc1Ch0,
+		&mem_cfg->DqMapCpu2DramMc1Ch1,
+		&mem_cfg->DqMapCpu2DramMc1Ch2,
+		&mem_cfg->DqMapCpu2DramMc1Ch3,
 	};
 
-	const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramCh0);
+	const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0);
 
 	_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!");
 
@@ -130,17 +130,17 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da
 				const struct mb_cfg *mb_cfg)
 {
 	void *dqs_upds[MRC_CHANNELS] = {
-		&mem_cfg->DqsMapCpu2DramCh0,
-		&mem_cfg->DqsMapCpu2DramCh1,
-		&mem_cfg->DqsMapCpu2DramCh2,
-		&mem_cfg->DqsMapCpu2DramCh3,
-		&mem_cfg->DqsMapCpu2DramCh4,
-		&mem_cfg->DqsMapCpu2DramCh5,
-		&mem_cfg->DqsMapCpu2DramCh6,
-		&mem_cfg->DqsMapCpu2DramCh7,
+		&mem_cfg->DqsMapCpu2DramMc0Ch0,
+		&mem_cfg->DqsMapCpu2DramMc0Ch1,
+		&mem_cfg->DqsMapCpu2DramMc0Ch2,
+		&mem_cfg->DqsMapCpu2DramMc0Ch3,
+		&mem_cfg->DqsMapCpu2DramMc1Ch0,
+		&mem_cfg->DqsMapCpu2DramMc1Ch1,
+		&mem_cfg->DqsMapCpu2DramMc1Ch2,
+		&mem_cfg->DqsMapCpu2DramMc1Ch3,
 	};
 
-	const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramCh0);
+	const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0);
 
 	_Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!");