diff options
| author | Kapil Porwal <kapilporwal@google.com> | 2024-11-15 11:36:36 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-18 02:55:03 +0000 |
| commit | 34f54e4e4b13c657f39ddec65e999f9df8295095 (patch) | |
| tree | ef8331bb739f2cb95e05b2163f38022b578941c1 /src | |
| parent | 640a41f3ee938b794b140218921e0fd63b1d9235 (diff) | |
mb/google/trulo: Fix invalid GPE route configuration
GPE route for GPE0_DW0 was not being programmed (i.e. 0) which made it
route to GPP_B since a value of 0 means GPP_B. GPE route for GPE0_DW1
is also being programmed to GPP_B which makes the overall configuration
invalid.
The fix is to program the GPE0_DW0 route to a GPIO group which is not
already being used for GPE0_DW1 & GPE0_DW2 i.e. GPP_A.
Additionally, the common GPE route configuration is moved to baseboard.
BUG=b:378455259
TEST=Verify wake from S0ix when charger is connected
Change-Id: I674cf7db160b6bc1ec3d620f9c99ea91041c48bb
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85157
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src')
3 files changed, 5 insertions, 8 deletions
diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb index 6016a7f03a..3090bb54fa 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/trulo/devicetree.cb @@ -1,5 +1,10 @@ chip soc/intel/alderlake + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_A" + register "pmc_gpe0_dw1" = "GPP_B" + register "pmc_gpe0_dw2" = "GPP_F" + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x000c0201" diff --git a/src/mainboard/google/brya/variants/orisa/overridetree.cb b/src/mainboard/google/brya/variants/orisa/overridetree.cb index 26b8c1d2f9..e49714297a 100644 --- a/src/mainboard/google/brya/variants/orisa/overridetree.cb +++ b/src/mainboard/google/brya/variants/orisa/overridetree.cb @@ -19,10 +19,6 @@ end chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" - # GPE configuration - register "pmc_gpe0_dw1" = "GPP_B" - register "pmc_gpe0_dw2" = "GPP_F" - # S0ix enable register "s0ix_enable" = "true" diff --git a/src/mainboard/google/brya/variants/trulo/overridetree.cb b/src/mainboard/google/brya/variants/trulo/overridetree.cb index ae18a0f101..631fe7b8d8 100644 --- a/src/mainboard/google/brya/variants/trulo/overridetree.cb +++ b/src/mainboard/google/brya/variants/trulo/overridetree.cb @@ -19,10 +19,6 @@ end chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" - # GPE configuration - register "pmc_gpe0_dw1" = "GPP_B" - register "pmc_gpe0_dw2" = "GPP_F" - # S0ix enable register "s0ix_enable" = "true" |