diff options
| author | Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> | 2021-03-05 15:06:43 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-15 06:25:29 +0000 |
| commit | 285f20a7f0a42d1c1b173d7c9b9d0c276519321d (patch) | |
| tree | 42b590b0b6b6d5f6340774c0a21e9fd3418e55d1 /src | |
| parent | 81f70a9fdfe125afac0ef8673b97c2aff9b511da (diff) | |
mb/google/hatch: Update DPTF parameters for genesis
update the DPTF parameters received from the thermal team.
BUG=b:181627614
TEST=emerge-ambassador coreboot
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ied6b71d9285662a70446af2e781b630e184c3b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joe Tessler <jrt@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/hatch/variants/genesis/overridetree.cb | 31 |
1 files changed, 14 insertions, 17 deletions
diff --git a/src/mainboard/google/hatch/variants/genesis/overridetree.cb b/src/mainboard/google/hatch/variants/genesis/overridetree.cb index 1c05f52817..20a07cae33 100644 --- a/src/mainboard/google/hatch/variants/genesis/overridetree.cb +++ b/src/mainboard/google/hatch/variants/genesis/overridetree.cb @@ -243,38 +243,35 @@ chip soc/intel/cannonlake chip drivers/intel/dptf ## Active Policy register "policies.active[0]" = "{.target=DPTF_CPU, - .thresholds={TEMP_PCT(90, 85), - TEMP_PCT(85, 75), - TEMP_PCT(80, 65), - TEMP_PCT(75, 55), - TEMP_PCT(70, 45),}}" + .thresholds={TEMP_PCT(94, 0),}}" register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0, - .thresholds={TEMP_PCT(50, 85), - TEMP_PCT(47, 75), - TEMP_PCT(45, 65), - TEMP_PCT(42, 55), - TEMP_PCT(39, 45),}}" + .thresholds={TEMP_PCT(72, 90), + TEMP_PCT(68, 80), + TEMP_PCT(62, 70), + TEMP_PCT(54, 60), + TEMP_PCT(46, 50), + TEMP_PCT(39, 40),}}" ## Passive Policy - register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 93, 5000)" - register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 65, 6000)" + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000)" ## Critical Policy register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)" - register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN)" ## Power Limits Control # PL1 is fixed at 15W, avg over 28-32s interval - # 25-64W PL2 in 1000mW increments, avg over 28-32s interval + # 51-51W PL2 in 1000mW increments, avg over 28-32s interval register "controls.power_limits.pl1" = "{ .min_power = 15000, .max_power = 15000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, - .granularity = 200,}" + .granularity = 125,}" register "controls.power_limits.pl2" = "{ - .min_power = 25000, - .max_power = 64000, + .min_power = 51000, + .max_power = 51000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 1000,}" |