diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-06-10 22:25:48 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-29 09:46:01 +0000 |
| commit | 248dbe0908f1b934d465550987a2497cd6593b4b (patch) | |
| tree | 5684a8cb336082f4128c4b9090b3705d5bab44bc /src | |
| parent | 9f91ced9ddaeed6730e53954260d82f665269cb0 (diff) | |
soc/intel/alderlake: Trigger cse_fw_sync before DRAM Init
The patch enables cse_fw_sync() before DRAM initialization.
cse_fw_sync() sends HECI commands in order to set CSE's boot partition
and to trigger CSE firmware update.
As part of CSE firmware update, coreboot sends HMRPFO_ENABLE HECI
command. Since CSE supports the command after DRAM Initialization,
cse_fw_sync() is called after DRAM initialization.
Starting from CSE Litev16.0.15.1545, CSE support HMRFPO_ENABLE command
before DRAM initialization too. So, cse_fw_sync() is called before DRAM
initialization.
BUG=b:175516533
TEST=Dependency with CSE Litev16.0.15.1545 integration
Change-Id: Iad7403650df8bc4e40aa6e48ccfeba95a5789a2d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55364
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 14 |
1 files changed, 4 insertions, 10 deletions
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index e84eca8ed4..d33d21f1aa 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -129,6 +129,9 @@ void mainboard_romstage_entry(void) s3wake = pmc_fill_power_state(ps) == ACPI_S3; + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && !s3wake) + cse_fw_sync(); + /* * Set low maximum temp threshold value used for dynamic thermal sensor * shutdown consideration. @@ -140,15 +143,6 @@ void mainboard_romstage_entry(void) fsp_memory_init(s3wake); pmc_set_disb(); - if (!s3wake) { - /* - * cse_fw_sync() must be called after DRAM initialization as - * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync()) - * is expected to be executed after DRAM initialization. - */ - if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) - cse_fw_sync(); - + if (!s3wake) save_dimm_info(); - } } |