aboutsummaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorPatrick Rudolph <patrick.rudolph@9elements.com>2023-12-21 14:49:36 +0100
committerFelix Held <felix-coreboot@felixheld.de>2024-04-12 18:19:00 +0000
commit220bd26b6e2ae6608fb588146fef2013db84fedc (patch)
tree7ceb87148ade381240e9648379659ee46619d957 /src
parentd81324eb74d880bcb434a74f337f9b08a0057c2f (diff)
nb/intel/sandybridge/raminit: Only write register on Ivy Bridge
Only write register WMM_READ_CONFIG on Ivy Bridge as it's reserved on Sandy Bridge. Tested on Lenovo X220: Still boots and runs fine. Change-Id: Ie14ea06d744b1a8368d32803c6c1ccfb1262532e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79761 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src')
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index d6d545c10e..fea3ca4e8f 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -2809,8 +2809,8 @@ void final_registers(ramctr_timing *ctrl)
int t3_ns;
u32 r32;
- /* FIXME: This register only exists on Ivy Bridge */
- mchbar_write32(WMM_READ_CONFIG, 0x46);
+ if (IS_IVY_CPU(ctrl->cpu))
+ mchbar_write32(WMM_READ_CONFIG, 0x46);
FOR_ALL_CHANNELS {
union tc_othp_reg tc_othp = {