diff options
| author | Malik_Hsu <malik_hsu@wistron.corp-partner.google.com> | 2021-09-15 13:22:23 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-09-17 22:20:05 +0000 |
| commit | 1ad9ff815610fd94820a9f1c6d4426ae49ba2846 (patch) | |
| tree | a6bb3143379f2a886d64aee8e0a40c257a298c9d /src | |
| parent | 8d46db20a3605606e9f6b25512aa3569ce818746 (diff) | |
mb/google/brya/primus: add NVMe power and reset pin to early_gpio_table
NVMe needs extra time to run boot process, enable power and deassert
reset for NVMe earlier in the boot flow that primus can successfully
boot into OS with non-serial coreboot.
BUG=b:199967106
TEST=USE="project_primus" emerge-brya coreboot and verify it builds
without error.
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I9c66efe96515347502d059556052c764c1be5d09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/primus/gpio.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/primus/gpio.c b/src/mainboard/google/brya/variants/primus/gpio.c index 20911680d0..33a0f025cc 100644 --- a/src/mainboard/google/brya/variants/primus/gpio.c +++ b/src/mainboard/google/brya/variants/primus/gpio.c @@ -94,6 +94,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_D1, 0, DEEP), /* D2 : ISH_GP2 ==> EN_FP_PWR */ PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* D18 : UART1_TXD ==> SD_PE_RST_L */ PAD_CFG_GPO(GPP_D18, 0, PLTRST), /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */ @@ -110,6 +112,11 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* H13 : I2C7_SCL ==> EN_PP3300_SD */ PAD_CFG_GPO(GPP_H13, 1, PLTRST), + /* B4 : PROC_GP3 ==> SSD_PERST_L + * SSD_PERST_L is released after EN_PP3300_SSD is asserted; the + * power rails take some time to come up. + */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) |