summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorEdward O'Callaghan <quasisec@google.com>2020-07-01 18:47:47 +1000
committerEdward O'Callaghan <quasisec@chromium.org>2020-07-03 00:03:23 +0000
commit181c3f846ba6d73928e32d168f0de82dad9fcdb6 (patch)
treeb7c763bf8a0d8807b7e0f0072326cbfb6f9935e9 /src
parent78a8c85a47416991f71f21dba38d64d29b90f4f6 (diff)
mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in Kaisa
BUG=b:160296661 BRANCH=none TEST=none Change-Id: Id5a03f2cbdca2723ab1882c619d2d34387996b27 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42973 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/hatch/variants/kaisa/overridetree.cb12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
index 1068b590e5..eb177f2696 100644
--- a/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/kaisa/overridetree.cb
@@ -81,6 +81,18 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
+ # Bitmap for Wake Enable on USB attach/detach
+ register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+ USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(5) | \
+ USB_PORT_WAKE_ENABLE(6)"
+ register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \
+ USB_PORT_WAKE_ENABLE(2) | \
+ USB_PORT_WAKE_ENABLE(3) | \
+ USB_PORT_WAKE_ENABLE(5) | \
+ USB_PORT_WAKE_ENABLE(6)"
+
# Enable eMMC HS400
register "ScsEmmcHs400Enabled" = "1"