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authorMarc Jones <marcj303@gmail.com>2017-11-16 15:26:00 -0700
committerMarc Jones <marc@marcjonesconsulting.com>2017-11-23 00:34:01 +0000
commit17431abab00a0f4bd68edb0abab5e9980a1434e5 (patch)
tree9c365122206130cba4f9760a4facdb3729126d8e /src
parent8788fd63952b50e4692efbf75a21bf0608e4c01c (diff)
soc/amd/stoneyridge: Get entire DDR4 SPD
Set the SPD size to 512 to get the entire DDR4 SPD. Change-Id: I0bdf8101de22533b2f4337d3c9e4423d62e6c66d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/Kconfig4
-rw-r--r--src/soc/amd/stoneyridge/dimm_spd.c3
2 files changed, 6 insertions, 1 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 446c451f71..7f44883800 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -352,4 +352,8 @@ comment "AMD Firmware Directory Table set to location for 8MB ROM"
comment "AMD Firmware Directory Table set to location for 16MB ROM"
depends on AMD_FWM_POSITION_INDEX = 5
+config DIMM_SPD_SIZE
+ int
+ default 512 # DDR4
+
endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4
diff --git a/src/soc/amd/stoneyridge/dimm_spd.c b/src/soc/amd/stoneyridge/dimm_spd.c
index 13fd72fe25..d9f6355da0 100644
--- a/src/soc/amd/stoneyridge/dimm_spd.c
+++ b/src/soc/amd/stoneyridge/dimm_spd.c
@@ -40,7 +40,8 @@ AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2,
[info->SocketId][info->MemChannelId][info->DimmId];
if (spd_address == 0)
return AGESA_ERROR;
- int err = sb_read_spd(spd_address, (void *)info->Buffer, 128);
+ int err = sb_read_spd(spd_address, (void *)info->Buffer,
+ CONFIG_DIMM_SPD_SIZE);
if (err)
return AGESA_ERROR;
return AGESA_SUCCESS;