diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-12-09 12:32:12 +0100 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2022-12-12 01:28:33 +0000 |
| commit | 122e1dfe5d992788b636e803dd9aa76ba5497220 (patch) | |
| tree | 9fd2373adaf7a799544bc5b5c38f9ed0f33cc344 /src | |
| parent | 5a724a1adc40486bcfdc9db56029b683b8405413 (diff) | |
soc/intel/alderlake/Kconfig: Sort defaults alphabetically
"Argh! Lack of consistency! UNACCEPTABLE!" - Emotions
Swap the position of two lines so that defaults are listed in
alphabetical order according to the PCH type: M, N, P, S.
Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/alderlake/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 5b624d8ae1..5f24e37036 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -252,8 +252,8 @@ config MAX_PCIE_CLOCK_SRC int default 6 if SOC_INTEL_ALDERLAKE_PCH_M default 5 if SOC_INTEL_ALDERLAKE_PCH_N - default 18 if SOC_INTEL_ALDERLAKE_PCH_S default 10 if SOC_INTEL_ALDERLAKE_PCH_P + default 18 if SOC_INTEL_ALDERLAKE_PCH_S help With external clock buffer, Alderlake-P can support up to three additional source clocks. This is done by setting the corresponding GPIO pin(s) to native function to use as |