haswell: Export functions for CPU family+model and stepping

These are needed to enable workarounds/features on specific
CPU types and stepping.  The older northbridge function and
defines from sandybridge/ivybridge are removed.

Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61333
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4355
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

4 files changed, 34 insertions, 39 deletions

diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index e8c224944a..9ed00af632 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -24,8 +24,20 @@
 
 #include <arch/cpu.h>
 
+/* Haswell CPU types */
+#define HASWELL_FAMILY_MOBILE		0x306c0
+#define HASWELL_FAMILY_ULT		0x40650
+
+/* Haswell CPU steppings */
+#define HASWELL_STEPPING_MOBILE_A0	1
+#define HASWELL_STEPPING_MOBILE_B0	2
+#define HASWELL_STEPPING_MOBILE_C0	3
+#define HASWELL_STEPPING_MOBILE_D0	4
+#define HASWELL_STEPPING_ULT_B0		0
+#define HASWELL_STEPPING_ULT_C0		1
+
 /* Haswell bus clock is fixed at 100MHz */
-#define HASWELL_BCLK		100
+#define HASWELL_BCLK			100
 
 #define CORE_THREAD_COUNT_MSR		0x35
 #define IA32_FEATURE_CONTROL		0x3a
@@ -219,6 +231,11 @@ struct ramstage_cache {
 	char program[0];
 } __attribute__((packed));
 
+/* CPU identification */
+int haswell_family_model(void);
+int haswell_stepping(void);
+int haswell_is_ult(void);
+
 #endif
 
 #endif
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index adc99cfd48..f8d295e066 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -207,13 +207,23 @@ static const u8 power_limit_time_msr_to_sec[] = {
 	[0x11] = 128,
 };
 
+int haswell_family_model(void)
+{
+	return cpuid_eax(1) & 0x0fff0ff0;
+}
+
+int haswell_stepping(void)
+{
+	return cpuid_eax(1) & 0xf;
+}
+
 /* Dynamically determine if the part is ULT. */
-static int is_ult(void)
+int haswell_is_ult(void)
 {
 	static int ult = -1;
 
 	if (ult < 0)
-		ult = (cpuid_eax(1) > 0x40650);
+		ult = !!(haswell_family_model() == HASWELL_FAMILY_ULT);
 
 	return ult;
 }
@@ -308,7 +318,7 @@ static void initialize_vr_config(void)
 	msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold -  5A. */
 	msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */
 
-	if (is_ult())
+	if (haswell_is_ult())
 		msr.hi |= (1 <<  (62 - 32)); /* Enable PSI4 */
 	/* Leave the max instantaneous current limit (12:0) to default. */
 	wrmsr(MSR_VR_CURRENT_CONFIG, msr);
@@ -334,7 +344,7 @@ static void initialize_vr_config(void)
 	wrmsr(MSR_VR_MISC_CONFIG, msr);
 
 	/*  Configure VR_MISC_CONFIG2 MSR. */
-	if (is_ult()) {
+	if (haswell_is_ult()) {
 		msr = rdmsr(MSR_VR_MISC_CONFIG2);
 		msr.lo &= ~0xffff;
 		/* Allow CPU to control minimum voltage completely (15:8) and
@@ -521,7 +531,7 @@ static void configure_c_states(void)
 	wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr);
 
 	/* Haswell ULT only supoprts the 3-5 latency response registers.*/
-	if (is_ult()) {
+	if (haswell_is_ult()) {
 		/* C-state Interrupt Response Latency Control 3 - package C8 */
 		msr.hi = 0;
 		msr.lo = IRTL_VALID | IRTL_1024_NS |
@@ -698,7 +708,7 @@ static void bsp_init_before_ap_bringup(struct bus *cpu_bus)
 
 	initialize_vr_config();
 
-	if (is_ult()) {
+	if (haswell_is_ult()) {
 		calibrate_24mhz_bclk();
 		configure_pch_power_sharing();
 	}
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 7d451a91da..c9e10ed4f5 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -26,23 +26,6 @@
 #define HASWELL_DESKTOP	1
 #define HASWELL_SERVER	2
 
-/* Device ID for SandyBridge and IvyBridge */
-#define BASE_REV_SNB	0x00
-#define BASE_REV_IVB	0x50
-#define BASE_REV_MASK	0x50
-
-/* SandyBridge CPU stepping */
-#define SNB_STEP_D0	(BASE_REV_SNB + 5) /* Also J0 */
-#define SNB_STEP_D1	(BASE_REV_SNB + 6)
-#define SNB_STEP_D2	(BASE_REV_SNB + 7) /* Also J1/Q0 */
-
-/* IvyBridge CPU stepping */
-#define IVB_STEP_A0	(BASE_REV_IVB + 0)
-#define IVB_STEP_B0	(BASE_REV_IVB + 2)
-#define IVB_STEP_C0	(BASE_REV_IVB + 4)
-#define IVB_STEP_K0	(BASE_REV_IVB + 5)
-#define IVB_STEP_D0	(BASE_REV_IVB + 6)
-
 /* Intel Enhanced Debug region */
 #define IED_SIZE	CONFIG_IED_REGION_SIZE
 
@@ -215,7 +198,6 @@ struct ied_header {
 #ifdef __SMM__
 void intel_northbridge_haswell_finalize_smm(void);
 #else /* !__SMM__ */
-int bridge_silicon_revision(void);
 void haswell_early_initialization(int chipset_type);
 void haswell_late_initialization(void);
 
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index be1b61456b..bdf87b1616 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -39,20 +39,6 @@
 #include "chip.h"
 #include "haswell.h"
 
-static int bridge_revision_id = -1;
-
-int bridge_silicon_revision(void)
-{
-	if (bridge_revision_id < 0) {
-		uint8_t stepping = cpuid_eax(1) & 0xf;
-		uint8_t bridge_id = pci_read_config16(
-			dev_find_slot(0, PCI_DEVFN(0, 0)),
-			PCI_DEVICE_ID) & 0xf0;
-		bridge_revision_id = bridge_id | stepping;
-	}
-	return bridge_revision_id;
-}
-
 static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
 {
 	u32 pciexbar_reg;