diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2021-08-25 10:38:34 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-10-14 13:06:21 +0000 |
| commit | 0c3aaba9561ac794c6bab3baa0465a0e1884f7f6 (patch) | |
| tree | 5e376deb40c6141e15340757a4efea74f996b7ff /src | |
| parent | f343ed42ebeac7d28fb751635a6771731baae554 (diff) | |
mb/siemens/mc_ehl2: Enable PCI devices
Correct the remaining PCI devices, differing from the ehl1 mainboard.
Change-Id: I8112fa5ea86e879741061798530150701b759156
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb index 062ac5ff83..06fdf0a180 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl2/devicetree.cb @@ -161,7 +161,7 @@ chip soc/intel/elkhartlake device pci 11.6 off end # Intel PSE IS20 device pci 11.7 off end # Intel PSE IS21 - device pci 12.0 off end # GSPI2 + device pci 12.0 on end # GSPI2 device pci 12.3 on end # Management Engine UMA Access device pci 12.4 on end # Management Engine PTT DMA Controller device pci 12.5 off end # UFS0 @@ -177,7 +177,7 @@ chip soc/intel/elkhartlake device pci 14.0 on end # USB3.1 xHCI device pci 14.1 off end # USB3.1 xDCI (OTG) - device pci 15.0 off end # I2C0 + device pci 15.0 on end # I2C0 device pci 15.1 on end # I2C1 device pci 15.2 on # I2C2 # Enable external RTC chip @@ -195,7 +195,7 @@ chip soc/intel/elkhartlake device i2c 0x32 on end # RTC RX6110 SA end end - device pci 15.3 off end # I2C3 + device pci 15.3 on end # I2C3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 on end # Management Engine Interface 2 @@ -213,7 +213,7 @@ chip soc/intel/elkhartlake device pci 18.6 off end # Intel PSE QEP3 device pci 19.0 on end # I2C4 - device pci 19.1 off end # I2C5 + device pci 19.1 on end # I2C5 device pci 19.2 on end # UART2 device pci 1a.0 on end # eMMC |