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authorFelix Held <felix-coreboot@felixheld.de>2021-11-23 10:19:28 +0100
committerFelix Held <felix-coreboot@felixheld.de>2021-11-25 11:08:36 +0000
commit0bc4684f89e927c80c5af66ff4d223e89a8425c1 (patch)
tree73e3d3a1bab7879845ae0949939d9f1ec81d3b3a /src
parenta7190ef2ec2081a5415d3078360a04f013face9f (diff)
soc/amd/stoneyridge: use SOC_AMD_COMMON_BLOCK_ACPI_GPIO
Stoneyridge uses the same GPIO bank peripheral as Picasso and Cezanne so we can use the common AMD SoC GPIO ACPI code. TEST=none Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/stoneyridge/Kconfig1
-rw-r--r--src/soc/amd/stoneyridge/acpi.c100
2 files changed, 1 insertions, 100 deletions
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 50e66b0a79..769a61533b 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -24,6 +24,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_PI
select SOC_AMD_COMMON
select SOC_AMD_COMMON_BLOCK_ACPI
+ select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM
select SOC_AMD_COMMON_BLOCK_AOAC
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 918ba5e6d7..b2cc20b77d 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -157,103 +157,3 @@ void generate_cpu_entries(const struct device *device)
acpigen_write_name_integer("PCNT", cores);
acpigen_pop_len();
}
-
-static void acpigen_soc_get_gpio_in_local5(uintptr_t addr)
-{
- /*
- * Store (\_SB.GPR2 (addr), Local5)
- * \_SB.GPR2 is used to read control byte 2 from control register.
- * / It is defined in gpio_lib.asl.
- */
- acpigen_write_store();
- acpigen_emit_namestring("\\_SB.GPR2");
- acpigen_write_integer(addr);
- acpigen_emit_byte(LOCAL5_OP);
-}
-
-static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask)
-{
- if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
- printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
- " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
- return -1;
- }
- uintptr_t addr = gpio_get_address(gpio_num);
-
- acpigen_soc_get_gpio_in_local5(addr);
-
- /* If (And (Local5, mask)) */
- acpigen_write_if_and(LOCAL5_OP, mask);
-
- /* Store (One, Local0) */
- acpigen_write_store_ops(ONE_OP, LOCAL0_OP);
-
- /* Else */
- acpigen_write_else();
-
- /* Store (Zero, Local0) */
- acpigen_write_store_ops(ZERO_OP, LOCAL0_OP);
-
- acpigen_pop_len(); /* Else */
-
- return 0;
-}
-
-static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val)
-{
- if (gpio_num >= SOC_GPIO_TOTAL_PINS) {
- printk(BIOS_WARNING, "Warning: Pin %d should be smaller than"
- " %d\n", gpio_num, SOC_GPIO_TOTAL_PINS);
- return -1;
- }
- uintptr_t addr = gpio_get_address(gpio_num);
-
- /* Store (0x40, Local0) */
- acpigen_write_store();
- acpigen_write_integer(GPIO_PIN_OUT);
- acpigen_emit_byte(LOCAL0_OP);
-
- acpigen_soc_get_gpio_in_local5(addr);
-
- if (val) {
- /* Or (Local5, GPIO_PIN_OUT, Local5) */
- acpigen_write_or(LOCAL5_OP, LOCAL0_OP, LOCAL5_OP);
- } else {
- /* Not (GPIO_PIN_OUT, Local6) */
- acpigen_write_not(LOCAL0_OP, LOCAL6_OP);
-
- /* And (Local5, Local6, Local5) */
- acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP);
- }
-
- /*
- * SB.GPW2 (addr, Local5)
- * \_SB.GPW2 is used to write control byte in control register
- * / byte 2. It is defined in gpio_lib.asl.
- */
- acpigen_emit_namestring("\\_SB.GPW2");
- acpigen_write_integer(addr);
- acpigen_emit_byte(LOCAL5_OP);
-
- return 0;
-}
-
-int acpigen_soc_read_rx_gpio(unsigned int gpio_num)
-{
- return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_IN);
-}
-
-int acpigen_soc_get_tx_gpio(unsigned int gpio_num)
-{
- return acpigen_soc_get_gpio_val(gpio_num, GPIO_PIN_OUT);
-}
-
-int acpigen_soc_set_tx_gpio(unsigned int gpio_num)
-{
- return acpigen_soc_set_gpio_val(gpio_num, 1);
-}
-
-int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
-{
- return acpigen_soc_set_gpio_val(gpio_num, 0);
-}