diff options
| author | John Zhao <john.zhao@intel.com> | 2020-06-30 21:26:55 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-12 19:41:47 +0000 |
| commit | 025af31423953b04dcdcf658dc82d099705a8942 (patch) | |
| tree | 480e02dd3c7aed77d65514aae9ee2e00606c46e1 /src | |
| parent | 35a30c55267a65770714f16192c0de78b0dca92f (diff) | |
mb/intel/tglrvp: Add SMI handler for tglrvp
This change adds SMI handler for SCI, S3/S5 wake up and LID closed
events on tglrvp platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0bc72f164e86f1921e0cad39f9749e8e3be0778f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/tglrvp/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/smihandler.c | 28 |
2 files changed, 30 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc index fbdac4d1eb..065bd4c3a2 100644 --- a/src/mainboard/intel/tglrvp/Makefile.inc +++ b/src/mainboard/intel/tglrvp/Makefile.inc @@ -11,6 +11,8 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c +smm-y += smihandler.c + ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c ramstage-y += board_id.c diff --git a/src/mainboard/intel/tglrvp/smihandler.c b/src/mainboard/intel/tglrvp/smihandler.c new file mode 100644 index 0000000000..8c9444cb59 --- /dev/null +++ b/src/mainboard/intel/tglrvp/smihandler.c @@ -0,0 +1,28 @@ +/* + * + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <cpu/x86/smm.h> +#include <ec/google/chromeec/smm.h> +#include <intelblocks/smihandler.h> +#include <baseboard/ec.h> + +void mainboard_smi_espi_handler(void) +{ + chromeec_smi_process_events(); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, + MAINBOARD_EC_S5_WAKE_EVENTS); +} + +int mainboard_smi_apmc(u8 apmc) +{ + chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, + MAINBOARD_EC_SMI_EVENTS); + return 0; +} |