diff options
| author | Rex-BC Chen <rex-bc.chen@mediatek.com> | 2021-05-10 20:06:35 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-05-13 01:43:57 +0000 |
| commit | 00b43c98437484c59da0d1332936ee9a15d453fe (patch) | |
| tree | bd69701cac3ee266def3ff30b92575d37b22f971 /src | |
| parent | 8c3b747ccffc6a0fda8bde74caaf685dde78930f (diff) | |
soc/mediatek/mt8195: configure DMA buffer in DRAM
Set DRAM DMA to be non-cacheable to load blob correctly.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I819d40431fc7c9e7549686736d9e70de1c1982f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54052
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/mediatek/mt8195/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/mediatek/mt8195/mmu_operations.c | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 67ceed3603..a04ccf4a19 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -26,6 +26,7 @@ romstage-y += emi.c romstage-y += ../common/flash_controller.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/i2c.c i2c.c +romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-y += ../common/pll.c pll.c romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8195/mmu_operations.c b/src/soc/mediatek/mt8195/mmu_operations.c index 7018093dd9..de6e8bcdf9 100644 --- a/src/soc/mediatek/mt8195/mmu_operations.c +++ b/src/soc/mediatek/mt8195/mmu_operations.c @@ -29,3 +29,10 @@ void mtk_soc_disable_l2c_sram(void) MP0_CLUSTER_CFG0_L3_SHARE_PRE_EN, 0); dsb(); } + +/* mtk_soc_after_dram is called in romstage */ +void mtk_soc_after_dram(void) +{ + mmu_config_range(_dram_dma, REGION_SIZE(dram_dma), + NONSECURE_UNCACHED_MEM); +} |