summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
authorAnand Vaikar <a.vaikar2021@gmail.com>2024-01-05 14:27:02 +0530
committerFelix Held <felix-coreboot@felixheld.de>2024-01-15 13:17:33 +0000
commitd873d3a7ec6d39a792fc08bab4f24d7957866609 (patch)
tree00170e0b5dc60d6f8460315c3190f60ec2da12c3 /src
parentcf960a320fa1701430e4424829e3882a5a6578f1 (diff)
src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size
The PCIE MMCONFIG base address value and size is updated correctly to access the PCIE config space registers. TEST=Verified that PCIE enumeration takes place in boot log and config space registers are accessible. Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79832 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/soc/amd/glinda/Kconfig4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig
index ac0c96b157..b9760489d3 100644
--- a/src/soc/amd/glinda/Kconfig
+++ b/src/soc/amd/glinda/Kconfig
@@ -234,10 +234,10 @@ config RO_REGION_ONLY
default "apu/amdfw"
config ECAM_MMCONF_BASE_ADDRESS
- default 0xF8000000
+ default 0xE0000000
config ECAM_MMCONF_BUS_NUMBER
- default 64
+ default 256
config MAX_CPUS
int