From d873d3a7ec6d39a792fc08bab4f24d7957866609 Mon Sep 17 00:00:00 2001 From: Anand Vaikar Date: Fri, 5 Jan 2024 14:27:02 +0530 Subject: src/soc/amd/glinda: Update the PCIE MMCONFIG base address and size The PCIE MMCONFIG base address value and size is updated correctly to access the PCIE config space registers. TEST=Verified that PCIE enumeration takes place in boot log and config space registers are accessible. Change-Id: Ifa8377df7a2973a88d414c217b5ed114c8ae5cc3 Signed-off-by: Anand Vaikar Reviewed-on: https://review.coreboot.org/c/coreboot/+/79832 Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/glinda/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src') diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index ac0c96b157..b9760489d3 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -234,10 +234,10 @@ config RO_REGION_ONLY default "apu/amdfw" config ECAM_MMCONF_BASE_ADDRESS - default 0xF8000000 + default 0xE0000000 config ECAM_MMCONF_BUS_NUMBER - default 64 + default 256 config MAX_CPUS int -- cgit v1.2.3