diff options
| author | Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> | 2020-08-27 16:41:42 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-09-23 18:52:28 +0000 |
| commit | ca128a0eb42dfc41c80aef9659dae06274dd65b3 (patch) | |
| tree | 48f88f06f62ce40b9e9e5b82031ae2900c2b6c95 /src | |
| parent | 5b7daa224cb035f87c3b71105bb453849c7d54d4 (diff) | |
mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVP
BUG=none
TEST=Build for Tigerlake RVP and boot to OS. Test if following sysfs is populated.
cat /sys/devices/system/cpu/intel_pstate/
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Ie3d9691e149a6fbc19c6691896126d04c680fde3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45609
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index a2d297dc79..84b965e605 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -115,6 +115,9 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c381d2ef7d..417f23f83f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -109,6 +109,9 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable S0ix register "s0ix_enable" = "1" |