From ca128a0eb42dfc41c80aef9659dae06274dd65b3 Mon Sep 17 00:00:00 2001 From: Shreesh Chhabbi Date: Thu, 27 Aug 2020 16:41:42 -0700 Subject: mb/intel/tglrvp: Enable Intel Speed Shift Technology for Tigerlake RVP BUG=none TEST=Build for Tigerlake RVP and boot to OS. Test if following sysfs is populated. cat /sys/devices/system/cpu/intel_pstate/ Signed-off-by: Shreesh Chhabbi Change-Id: Ie3d9691e149a6fbc19c6691896126d04c680fde3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45609 Reviewed-by: Shreesh Chhabbi Reviewed-by: Ravishankar Sarawadi Reviewed-by: Srinidhi N Kaushik Tested-by: build bot (Jenkins) --- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 3 +++ src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 3 +++ 2 files changed, 6 insertions(+) (limited to 'src') diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index a2d297dc79..84b965e605 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -115,6 +115,9 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable S0ix register "s0ix_enable" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index c381d2ef7d..417f23f83f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -109,6 +109,9 @@ chip soc/intel/tigerlake register "TcssXhciEn" = "1" register "TcssAuxOri" = "0" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable S0ix register "s0ix_enable" = "1" -- cgit v1.2.3