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authorAngel Pons <th3fanbus@gmail.com>2020-12-11 16:48:10 +0100
committerHung-Te Lin <hungte@chromium.org>2020-12-14 08:18:06 +0000
commit43e93d7df900ec3925812b903bd29677a9ed6f08 (patch)
tree8a978ebaabecf5fd6b3696d1ce78f2af80b171a6 /src
parentf0fd6aeecd74da20967817b66e1074bbb201372b (diff)
soc/intel/alderlake: Drop unreferenced devicetree settings
No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src')
-rw-r--r--src/soc/intel/alderlake/chip.h8
1 files changed, 0 insertions, 8 deletions
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 428fd4deeb..38d9671f60 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -146,12 +146,6 @@ struct soc_intel_alderlake_config {
/* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */
uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
- /* Integrated Sensor */
- uint8_t PchIshEnable;
-
- /* Heci related */
- uint8_t Heci3Enabled;
-
/* Gfx related */
enum {
IGD_SM_0MB = 0x00,
@@ -178,8 +172,6 @@ struct soc_intel_alderlake_config {
uint8_t InternalGfx;
uint8_t SkipExtGfxScan;
- uint32_t GraphicsConfigPtr;
-
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;