From 43e93d7df900ec3925812b903bd29677a9ed6f08 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 11 Dec 2020 16:48:10 +0100 Subject: soc/intel/alderlake: Drop unreferenced devicetree settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No mainboard uses these settings, nor does SoC code. Drop them. Change-Id: Ib4cf88a482f840edf16e2ac42e6ab61eccfba0aa Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/48566 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Furquan Shaikh Reviewed-by: Michael Niewöhner --- src/soc/intel/alderlake/chip.h | 8 -------- 1 file changed, 8 deletions(-) (limited to 'src') diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 428fd4deeb..38d9671f60 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -146,12 +146,6 @@ struct soc_intel_alderlake_config { /* PCIE RP Advanced Error Report: Enable (1) / Disable (0) */ uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; - /* Integrated Sensor */ - uint8_t PchIshEnable; - - /* Heci related */ - uint8_t Heci3Enabled; - /* Gfx related */ enum { IGD_SM_0MB = 0x00, @@ -178,8 +172,6 @@ struct soc_intel_alderlake_config { uint8_t InternalGfx; uint8_t SkipExtGfxScan; - uint32_t GraphicsConfigPtr; - /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; -- cgit v1.2.3