diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2014-01-27 16:39:17 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2014-01-28 19:54:49 +0100 |
| commit | 3674ccfa3ef9fe9317bc9f9b7231e3b55452f1c4 (patch) | |
| tree | 19cc70fc7cbcf07fc91509723341d5155608d272 /src | |
| parent | e6767674af95c7b5e9b508839b3aaf8b477921c4 (diff) | |
x86/mtrr: don't assume size of ROM cached during CAR mode
Romstage and ramstage can use 2 different values for the
amount of ROM to cache just under 4GiB in the address
space. Don't assume a cpu's romstage caching policy
for the ROM.
Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4846
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/include/cpu/x86/mtrr.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index bbcde8a658..9414687552 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -134,10 +134,6 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type); #define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12) -#if ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) * 1UL > CACHE_ROM_BASE * 1UL) -# error "CAR region (WB) and flash (WP) regions overlap." -#endif - #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif |