From 3674ccfa3ef9fe9317bc9f9b7231e3b55452f1c4 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Mon, 27 Jan 2014 16:39:17 -0600 Subject: x86/mtrr: don't assume size of ROM cached during CAR mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Romstage and ramstage can use 2 different values for the amount of ROM to cache just under 4GiB in the address space. Don't assume a cpu's romstage caching policy for the ROM. Change-Id: I689fdf4d1f78e9556b0bc258e05c7b9bb99c48e1 Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4846 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/include/cpu/x86/mtrr.h | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src') diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index bbcde8a658..9414687552 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -134,10 +134,6 @@ void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type); #define CACHE_ROM_BASE (((1<<20) - (CACHE_ROM_SIZE>>12))<<12) -#if ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) * 1UL > CACHE_ROM_BASE * 1UL) -# error "CAR region (WB) and flash (WP) regions overlap." -#endif - #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 # error "CONFIG_RAMTOP must be a power of 2" #endif -- cgit v1.2.3