diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-16 18:43:52 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-07-02 07:39:16 +0000 |
| commit | 21b71ce66b89f7bff7959027d971e9a7786bf219 (patch) | |
| tree | b5167a09b1edadb86ed490dca77e6e8579c37f08 /src | |
| parent | 10b65dcfc76f62bf97c93f4a8e51a2269e5c040e (diff) | |
src/nb: Fix non-local header treated as local
Change-Id: I8174d7b40008cfe4fba10fde4670682aac0ad078
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/northbridge/amd/lx/raminit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/gm45.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/report_platform.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/raminit.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_mrc.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/report_platform.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/romstage.c | 2 |
7 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index ab5c70f09f..5f83331861 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -19,7 +19,7 @@ #include <arch/io.h> #include <spd.h> #include <stddef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "raminit.h" #include "northbridge.h" diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 56c6fea64b..5373e5e733 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -17,7 +17,7 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#include "southbridge/intel/i82801ix/i82801ix.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #ifndef __ACPI__ diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index aed125c8bc..5b738440f5 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -16,7 +16,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/lynxpoint/pch.h" +#include <southbridge/intel/lynxpoint/pch.h> #include <arch/io.h> #include <cpu/x86/msr.h> #include "haswell.h" diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index bd2042e418..94d9af8855 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -56,7 +56,7 @@ typedef u32 device_t; #include "nehalem.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <southbridge/intel/ibexpeak/me.h> #if REAL #include <delay.h> diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 691452ca43..c7e6e1f79b 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -34,7 +34,7 @@ #include <security/vboot/vboot_common.h> /* Management Engine is in the southbridge */ -#include "southbridge/intel/bd82x6x/me.h" +#include <southbridge/intel/bd82x6x/me.h> /* * MRC scrambler seed offsets should be reserved in diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index d137e8b63b..6dd760d3c9 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -16,7 +16,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/bd82x6x/pch.h> #include <arch/io.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 61f5e4a50c..3bfefb9fc7 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -30,7 +30,7 @@ #include <halt.h> #include <security/tpm/tspi.h> #include <northbridge/intel/sandybridge/chip.h> -#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> static void early_pch_init(void) |