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authorScott Duplichan <scott@notabs.org>2011-05-15 21:18:59 +0000
committerMarc Jones <marc.jones@amd.com>2011-05-15 21:18:59 +0000
commite78ae24eb1003f5fa22bd54365025dda78f37dda (patch)
tree513d2b271dd3b7cd8f5e46aa464c91f20183153a /src
parent444c49c68c224ac5b88a6efd96d4d3b911347356 (diff)
Configure CIMx to use 33 MHz fast mode for SPD read.
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src')
-rw-r--r--src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
index 7efa5ecfe2..93e1c310e6 100644
--- a/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
+++ b/src/southbridge/amd/cimx_wrapper/sb800/SBPLATFORM.h
@@ -116,8 +116,8 @@ typedef union _PCI_ADDR {
#define cimHpetTimerDefault TRUE
#define cimHpetMsiDisDefault FALSE // Enable
#define cimIrConfigDefault 0x00 // Disable
-#define cimSpiFastReadEnableDefault 0x00 // Disable
-#define cimSpiFastReadSpeedDefault 0x00 // NULL
+#define cimSpiFastReadEnableDefault 0x01 // Enable
+#define cimSpiFastReadSpeedDefault 0x01 // 33 MHz
// GPP/AB Controller
#define cimNbSbGen2Default TRUE
#define cimAlinkPhyPllPowerDownDefault TRUE