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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-07-14 23:23:43 -0700
committerSubrata Banik <subrata.banik@intel.com>2020-07-20 03:59:46 +0000
commit9ea45ffb39f022207f8f5dc4640eb26164baf00b (patch)
tree5c85a67339f3a9eb3c205701f315813032f1b479 /src/vendorcode
parent45d5f8f163898f943679129416b5c0d93c61c407 (diff)
vendorcode/intel/fsp: Update Tiger Lake FSP Headers for FSP v3274
Update FSP headers for Tiger Lake platform generated based FSP version 3274. Compared to the current version 3197, v3274 adds most of the legacy UPDs in both FSPM and FSPS. BUG=b:159151231 BRANCH=none TEST=build and boot volteer proto2 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Change-Id: Id3f957aa9d9ad9710a3c930717c22f485699315e Reviewed-on: https://review.coreboot.org/c/coreboot/+/43473 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h1510
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h2475
2 files changed, 3808 insertions, 177 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
index ade6b03b3b..8f40c14067 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
@@ -66,9 +66,15 @@ typedef struct {
**/
UINT16 MemorySpdDataLen;
-/** Offset 0x004A - Reserved
+/** Offset 0x004A - Enable above 4GB MMIO resource support
+ Enable/disable above 4GB MMIO resource support
+ $EN_DIS
+**/
+ UINT8 EnableAbove4GBMmio;
+
+/** Offset 0x004B - Reserved
**/
- UINT8 Reserved0[2];
+ UINT8 Reserved0;
/** Offset 0x004C - MemorySpdPtr00
**/
@@ -214,9 +220,35 @@ typedef struct {
**/
UINT8 DqPinsInterleaved;
-/** Offset 0x0129 - Reserved
+/** Offset 0x0129 - Smram Mask
+ The SMM Regions AB-SEG and/or H-SEG reserved
+ 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both
+**/
+ UINT8 SmramMask;
+
+/** Offset 0x012A - MRC Fast Boot
+ Enables/Disable the MRC fast path thru the MRC
+ $EN_DIS
+**/
+ UINT8 MrcFastBoot;
+
+/** Offset 0x012B - Rank Margin Tool per Task
+ This option enables the user to execute Rank Margin Tool per major training step
+ in the MRC.
+ $EN_DIS
+**/
+ UINT8 RmtPerTask;
+
+/** Offset 0x012C - Training Trace
+ This option enables the trained state tracing feature in MRC. This feature will
+ print out the key training parameters state across major training steps.
+ $EN_DIS
+**/
+ UINT8 TrainTrace;
+
+/** Offset 0x012D - Reserved
**/
- UINT8 Reserved1[7];
+ UINT8 Reserved1[3];
/** Offset 0x0130 - Intel Enhanced Debug
DEPRECATED
@@ -230,9 +262,17 @@ typedef struct {
**/
UINT32 TsegSize;
-/** Offset 0x0138 - Reserved
+/** Offset 0x0138 - MMIO Size
+ Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
**/
- UINT8 Reserved2[3];
+ UINT16 MmioSize;
+
+/** Offset 0x013A - Probeless Trace
+ Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
+ This also requires IED to be enabled.
+ $EN_DIS
+**/
+ UINT8 ProbelessTrace;
/** Offset 0x013B - Enable SMBus
Enable/disable SMBus controller.
@@ -257,9 +297,31 @@ typedef struct {
**/
UINT8 PlatformDebugConsent;
-/** Offset 0x014D - Reserved
+/** Offset 0x014D - DCI Enable
+ Determine if to enable DCI debug from host
+ $EN_DIS
+**/
+ UINT8 DciEn;
+
+/** Offset 0x014E - DCI DbC Mode
+ Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both:
+ Set both USB2/3DBCEN; No Change: Comply with HW value
+ 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change
+**/
+ UINT8 DciDbcMode;
+
+/** Offset 0x014F - Enable DCI ModPHY Pwoer Gate
+ Enable ModPHY Pwoer Gate when DCI is enabled
+ $EN_DIS
**/
- UINT8 Reserved3[4];
+ UINT8 DciModphyPg;
+
+/** Offset 0x0150 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support
+ This BIOS option enables kernel and platform debug for USB3 interface over a UFP
+ Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting.
+ 0:Disabled, 1:Enabled, 2:No Change
+**/
+ UINT8 DciUsb3TypecUfpDbg;
/** Offset 0x0151 - PCH Trace Hub Mode
Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
@@ -268,9 +330,23 @@ typedef struct {
**/
UINT8 PchTraceHubMode;
-/** Offset 0x0152 - Reserved
+/** Offset 0x0152 - PCH Trace Hub Memory Region 0 buffer Size
+ Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 PchTraceHubMemReg0Size;
+
+/** Offset 0x0153 - PCH Trace Hub Memory Region 1 buffer Size
+ Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (PCH + CPU) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
**/
- UINT8 Reserved4[9];
+ UINT8 PchTraceHubMemReg1Size;
+
+/** Offset 0x0154 - Reserved
+**/
+ UINT8 Reserved2[7];
/** Offset 0x015B - State of X2APIC_OPT_OUT bit in the DMAR table
0=Disable/Clear, 1=Enable/Set
@@ -278,9 +354,15 @@ typedef struct {
**/
UINT8 X2ApicOptOut;
-/** Offset 0x015C - Reserved
+/** Offset 0x015C - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
+ 0=Disable/Clear, 1=Enable/Set
+ $EN_DIS
**/
- UINT8 Reserved5[4];
+ UINT8 DmaControlGuarantee;
+
+/** Offset 0x015D - Reserved
+**/
+ UINT8 Reserved3[3];
/** Offset 0x0160 - Base addresses for VT-d function MMIO access
Base addresses for VT-d MMIO access per VT-d engine
@@ -335,9 +417,11 @@ typedef struct {
**/
UINT8 InternalGfx;
-/** Offset 0x018B - Reserved
+/** Offset 0x018B - Aperture Size
+ Select the Aperture Size.
+ 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB
**/
- UINT8 Reserved6;
+ UINT8 ApertureSize;
/** Offset 0x018C - Board Type
MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
@@ -348,7 +432,14 @@ typedef struct {
/** Offset 0x018D - Reserved
**/
- UINT8 Reserved7[3];
+ UINT8 Reserved4;
+
+/** Offset 0x018E - DDR Frequency Limit
+ Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
+ 2133, 2400, 2667, 2933 and 0 for Auto.
+ 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
+**/
+ UINT16 DdrFreqLimit;
/** Offset 0x0190 - SA GV
System Agent dynamic frequency support and when enabled memory will be training
@@ -357,9 +448,17 @@ typedef struct {
**/
UINT8 SaGv;
-/** Offset 0x0191 - Reserved
+/** Offset 0x0191 - Memory Test on Warm Boot
+ Run Base Memory Test on Warm Boot
+ 0:Disable, 1:Enable
**/
- UINT8 Reserved8[2];
+ UINT8 MemTestOnWarmBoot;
+
+/** Offset 0x0192 - DDR Speed Control
+ DDR Frequency and Gear control for all SAGV points.
+ 0:Auto, 1:Manual
+**/
+ UINT8 DdrSpeedControl;
/** Offset 0x0193 - Rank Margin Tool
Enable/disable Rank Margin Tool.
@@ -399,9 +498,18 @@ typedef struct {
**/
UINT8 DisableDimmCh7;
-/** Offset 0x019C - Reserved
+/** Offset 0x019C - Scrambler Support
+ This option enables data scrambling in memory.
+ $EN_DIS
+**/
+ UINT8 ScramblerSupport;
+
+/** Offset 0x019D - SPD Profile Selected
+ Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP
+ Profile 1, 3=XMP Profile 2
+ 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2
**/
- UINT8 Reserved9[2];
+ UINT8 SpdProfileSelected;
/** Offset 0x019E - Memory Reference Clock
100MHz, 133MHz.
@@ -411,7 +519,104 @@ typedef struct {
/** Offset 0x019F - Reserved
**/
- UINT8 Reserved10[22];
+ UINT8 Reserved5;
+
+/** Offset 0x01A0 - Memory Voltage
+ DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
+ chips) in millivolts. <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
+ 0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
+ Volts, 1450:1.45 Volts, 1500:1.50 Volts, 1550:1.55 Volts, 1600:1.60 Volts, 1650:1.65 Volts
+**/
+ UINT16 VddVoltage;
+
+/** Offset 0x01A2 - Memory Ratio
+ Automatic or the frequency will equal ratio times reference clock. Set to Auto to
+ recalculate memory timings listed below.
+ 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+ UINT8 Ratio;
+
+/** Offset 0x01A3 - tCL
+ CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tCL;
+
+/** Offset 0x01A4 - tCWL
+ Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tCWL;
+
+/** Offset 0x01A5 - Reserved
+**/
+ UINT8 Reserved6;
+
+/** Offset 0x01A6 - tFAW
+ Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tFAW;
+
+/** Offset 0x01A8 - tRAS
+ RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tRAS;
+
+/** Offset 0x01AA - tRCD/tRP
+ RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used
+ if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+ UINT8 tRCDtRP;
+
+/** Offset 0x01AB - Reserved
+**/
+ UINT8 Reserved7;
+
+/** Offset 0x01AC - tREFI
+ Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tREFI;
+
+/** Offset 0x01AE - tRFC
+ Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tRFC;
+
+/** Offset 0x01B0 - tRRD
+ Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tRRD;
+
+/** Offset 0x01B1 - tRTP
+ Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal
+ values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tRTP;
+
+/** Offset 0x01B2 - tWR
+ Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
+ 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+ 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
+ 34:34, 40:40
+**/
+ UINT8 tWR;
+
+/** Offset 0x01B3 - tWTR
+ Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT8 tWTR;
+
+/** Offset 0x01B4 - NMode
+ System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
+**/
+ UINT8 NModeSupport;
/** Offset 0x01B5 - Enable Intel HD Audio (Azalia)
0: Disable, 1: Enable (Default) Azalia controller
@@ -432,9 +637,184 @@ typedef struct {
**/
UINT8 CpuTraceHubMode;
-/** Offset 0x01B8 - Reserved
+/** Offset 0x01B8 - CPU Trace Hub Memory Region 0
+ CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 CpuTraceHubMemReg0Size;
+
+/** Offset 0x01B9 - CPU Trace Hub Memory Region 1
+ CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB,
+ 128MB, 256MB, 512MB. Note : Limitation of total buffer size (CPU + PCH) is 512MB.
+ 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB
+**/
+ UINT8 CpuTraceHubMemReg1Size;
+
+/** Offset 0x01BA - Reserved
+**/
+ UINT8 Reserved8[13];
+
+/** Offset 0x01C7 - HECI Timeouts
+ 0: Disable, 1: Enable (Default) timeout check for HECI
+ $EN_DIS
+**/
+ UINT8 HeciTimeouts;
+
+/** Offset 0x01C8 - HECI1 BAR address
+ BAR address of HECI1
+**/
+ UINT32 Heci1BarAddress;
+
+/** Offset 0x01CC - HECI2 BAR address
+ BAR address of HECI2
+**/
+ UINT32 Heci2BarAddress;
+
+/** Offset 0x01D0 - HECI3 BAR address
+ BAR address of HECI3
+**/
+ UINT32 Heci3BarAddress;
+
+/** Offset 0x01D4 - HG dGPU Power Delay
+ HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is
+ 300=300 microseconds
+**/
+ UINT16 HgDelayAfterPwrEn;
+
+/** Offset 0x01D6 - HG dGPU Reset Delay
+ HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100
+ microseconds
+**/
+ UINT16 HgDelayAfterHoldReset;
+
+/** Offset 0x01D8 - MMIO size adjustment for AUTO mode
+ Positive number means increasing MMIO size, Negative value means decreasing MMIO
+ size: 0 (Default)=no change to AUTO mode MMIO size
+**/
+ UINT16 MmioSizeAdjustment;
+
+/** Offset 0x01DA - PCIe ASPM programming will happen in relation to the Oprom
+ Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default):
+ Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after
+ Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume
+ 0:Before, 1:After
+**/
+ UINT8 InitPcieAspmAfterOprom;
+
+/** Offset 0x01DB - Selection of the primary display device
+ 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics
+ 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics
+**/
+ UINT8 PrimaryDisplay;
+
+/** Offset 0x01DC - Selection of PSMI Region size
+ 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0
+ 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB
+**/
+ UINT8 PsmiRegionSize;
+
+/** Offset 0x01DD - Reserved
+**/
+ UINT8 Reserved9[3];
+
+/** Offset 0x01E0 - Temporary MMIO address for GMADR
+ Obsolete field now and it has been extended to 64 bit address, used GmAdr64
+**/
+ UINT32 GmAdr;
+
+/** Offset 0x01E4 - Temporary MMIO address for GTTMMADR
+ The reference code will use this as Temporary MMIO address space to access GTTMMADR
+ Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
+ to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
+ + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
+**/
+ UINT32 GttMmAdr;
+
+/** Offset 0x01E8 - Selection of iGFX GTT Memory size
+ 1=2MB, 2=4MB, 3=8MB, Default is 3
+ 1:2MB, 2:4MB, 3:8MB
+**/
+ UINT16 GttSize;
+
+/** Offset 0x01EA - Reserved
+**/
+ UINT8 Reserved10[98];
+
+/** Offset 0x024C - Enable/Disable MRC TXT dependency
+ When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
+ MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
+ $EN_DIS
+**/
+ UINT8 TxtImplemented;
+
+/** Offset 0x024D - Enable/Disable SA OcSupport
+ Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
+ $EN_DIS
+**/
+ UINT8 SaOcSupport;
+
+/** Offset 0x024E - GT slice Voltage Mode
+ 0(Default): Adaptive, 1: Override
+ 0: Adaptive, 1: Override
+**/
+ UINT8 GtVoltageMode;
+
+/** Offset 0x024F - Maximum GTs turbo ratio override
+ 0(Default)=Minimal/Auto, 60=Maximum
+**/
+ UINT8 GtMaxOcRatio;
+
+/** Offset 0x0250 - The voltage offset applied to GT slice
+ 0(Default)=Minimal, 1000=Maximum
+**/
+ UINT16 GtVoltageOffset;
+
+/** Offset 0x0252 - The GT slice voltage override which is applied to the entire range of GT frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtVoltageOverride;
+
+/** Offset 0x0254 - adaptive voltage applied during turbo frequencies
+ 0(Default)=Minimal, 2000=Maximum
+**/
+ UINT16 GtExtraTurboVoltage;
+
+/** Offset 0x0256 - voltage offset applied to the SA
+ 0(Default)=Minimal, 1000=Maximum
+**/
+ UINT16 SaVoltageOffset;
+
+/** Offset 0x0258 - PCIe root port Function number for Hybrid Graphics dGPU
+ Root port Index number to indicate which PCIe root port has dGPU
+**/
+ UINT8 RootPortIndex;
+
+/** Offset 0x0259 - Realtime Memory Timing
+ 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
+ realtime memory timing changes after MRC_DONE.
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 RealtimeMemoryTiming;
+
+/** Offset 0x025A - This is policy to control iTBT PCIe Multiple Segment setting.
+ When Disabled all the TBT PCIe RP are located at Segment0, When Enabled all the
+ TBT PCIe RP are located at Segment1. <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PcieMultipleSegmentEnabled;
+
+/** Offset 0x025B - Enable/Disable SA IPU
+ Enable(Default): Enable SA IPU, Disable: Disable SA IPU
+ $EN_DIS
**/
- UINT8 Reserved11[165];
+ UINT8 SaIpuEnable;
+
+/** Offset 0x025C - IPU IMR Configuration
+ 0:IPU Camera, 1:IPU Gen Default is 0
+ 0:IPU Camera, 1:IPU Gen
+**/
+ UINT8 SaIpuImrConfiguration;
/** Offset 0x025D - IMGU CLKOUT Configuration
The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
@@ -444,7 +824,7 @@ typedef struct {
/** Offset 0x0263 - Reserved
**/
- UINT8 Reserved12;
+ UINT8 Reserved11;
/** Offset 0x0264 - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -454,7 +834,7 @@ typedef struct {
/** Offset 0x0268 - Reserved
**/
- UINT8 Reserved13;
+ UINT8 Reserved12;
/** Offset 0x0269 - RpClockReqMsgEnable
**/
@@ -464,9 +844,15 @@ typedef struct {
**/
UINT8 RpPcieThresholdBytes[4];
-/** Offset 0x026E - Reserved
+/** Offset 0x026E - Selection of PSMI Support On/Off
+ 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support
+ $EN_DIS
+**/
+ UINT8 GtPsmiSupport;
+
+/** Offset 0x026F - Reserved
**/
- UINT8 Reserved14[3];
+ UINT8 Reserved13[2];
/** Offset 0x0271 - Program GPIOs for LFP on DDI port-A device
0=Disabled,1(Default)=eDP, 2=MIPI DSI
@@ -566,16 +952,76 @@ typedef struct {
/** Offset 0x0281 - Reserved
**/
- UINT8 Reserved15[126];
+ UINT8 Reserved14[121];
+
+/** Offset 0x02FA - DMI Max Link Speed
+ Auto (0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 Speed, Gen2(0x2):
+ Limit Link to Gen2 Speed, (Default) Gen3(0x3):Limit Link to Gen3 Speed
+ 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
+**/
+ UINT8 DmiMaxLinkSpeed;
+
+/** Offset 0x02FB - DMI Equalization Phase 2
+ DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
+ AUTO - Use the current default method
+ 0:Disable phase2, 1:Enable phase2, 2:Auto
+**/
+ UINT8 DmiGen3EqPh2Enable;
+
+/** Offset 0x02FC - DMI Gen3 Equalization Phase3
+ DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
+ HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
+ Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
+ EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just
+ Phase1), Disabled(0x4): Bypass Equalization Phase 3
+ 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
+**/
+ UINT8 DmiGen3EqPh3Method;
+
+/** Offset 0x02FD - Enable/Disable DMI GEN3 Static EQ Phase1 programming
+ Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
+ Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
+ $EN_DIS
+**/
+ UINT8 DmiGen3ProgramStaticEq;
+
+/** Offset 0x02FE - DeEmphasis control for DMI
+ DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB
+ 0: -6dB, 1: -3.5dB
+**/
+ UINT8 DmiDeEmphasis;
/** Offset 0x02FF - DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane
**/
UINT8 DmiGen3RootPortPreset[8];
-/** Offset 0x0307 - Reserved
+/** Offset 0x0307 - DMI Gen3 End port preset values per lane
+ Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
+**/
+ UINT8 DmiGen3EndPointPreset[8];
+
+/** Offset 0x030F - DMI Gen3 End port Hint values per lane
+ Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
+**/
+ UINT8 DmiGen3EndPointHint[8];
+
+/** Offset 0x0317 - DMI Gen3 RxCTLEp per-Bundle control
+ Range: 0-15, 0 is default for each bundle, must be specified based upon platform design
+**/
+ UINT8 DmiGen3RxCtlePeaking[4];
+
+/** Offset 0x031B - BIST on Reset
+ Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 BistOnReset;
+
+/** Offset 0x031C - Skip Stop PBET Timer Enable/Disable
+ Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
**/
- UINT8 Reserved16[22];
+ UINT8 SkipStopPbet;
/** Offset 0x031D - C6DRAM power gating feature
This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
@@ -585,9 +1031,35 @@ typedef struct {
**/
UINT8 EnableC6Dram;
-/** Offset 0x031E - Reserved
+/** Offset 0x031E - Over clocking support
+ Over clocking support; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 OcSupport;
+
+/** Offset 0x031F - Over clocking Lock
+ Over clocking Lock Enable/Disable; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 OcLock;
+
+/** Offset 0x0320 - Maximum Core Turbo Ratio Override
+ Maximum core turbo ratio override allows to increase CPU core frequency beyond the
+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
**/
- UINT8 Reserved17[5];
+ UINT8 CoreMaxOcRatio;
+
+/** Offset 0x0321 - Core voltage mode
+ Core voltage mode; <b>0: Adaptive</b>; 1: Override.
+ $EN_DIS
+**/
+ UINT8 CoreVoltageMode;
+
+/** Offset 0x0322 - Maximum clr turbo ratio override
+ Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
+ fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
+**/
+ UINT8 RingMaxOcRatio;
/** Offset 0x0323 - Hyper Threading Enable/Disable
Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b>
@@ -595,9 +1067,11 @@ typedef struct {
**/
UINT8 HyperThreading;
-/** Offset 0x0324 - Reserved
+/** Offset 0x0324 - Enable or Disable CPU Ratio Override
+ Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
**/
- UINT8 Reserved18;
+ UINT8 CpuRatioOverride;
/** Offset 0x0325 - CPU ratio value
CPU ratio value. Valid Range 0 to 63
@@ -611,9 +1085,12 @@ typedef struct {
**/
UINT8 BootFrequency;
-/** Offset 0x0327 - Reserved
+/** Offset 0x0327 - Number of active cores
+ Number of active cores(Depends on Number of cores). <b>0: All</b>;<b>1: 1 </b>;<b>2:
+ 2 </b>;<b>3: 3 </b>
+ 0:All, 1:1, 2:2, 3:3
**/
- UINT8 Reserved19;
+ UINT8 ActiveCoreCount;
/** Offset 0x0328 - Processor Early Power On Configuration FCLK setting
<b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.-
@@ -622,9 +1099,12 @@ typedef struct {
**/
UINT8 FClkFrequency;
-/** Offset 0x0329 - Reserved
+/** Offset 0x0329 - Set JTAG power in C10 and deeper power states
+ False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10
+ and deeper power states for debug purpose. <b>0: False</b>; 1: True.
+ 0: False, 1: True
**/
- UINT8 Reserved20;
+ UINT8 JtagC10PowerGateDisable;
/** Offset 0x032A - Enable or Disable VMX
Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
@@ -632,9 +1112,111 @@ typedef struct {
**/
UINT8 VmxEnable;
-/** Offset 0x032B - Reserved
+/** Offset 0x032B - AVX2 Ratio Offset
+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+ UINT8 Avx2RatioOffset;
+
+/** Offset 0x032C - AVX3 Ratio Offset
+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+ UINT8 Avx3RatioOffset;
+
+/** Offset 0x032D - BCLK Adaptive Voltage Enable
+ When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
+ Disable;<b> 1: Enable
+ $EN_DIS
+**/
+ UINT8 BclkAdaptiveVoltage;
+
+/** Offset 0x032E - core voltage override
+ The core voltage override which is applied to the entire range of cpu core frequencies.
+ Valid Range 0 to 2000
+**/
+ UINT16 CoreVoltageOverride;
+
+/** Offset 0x0330 - Core Turbo voltage Adaptive
+ Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 CoreVoltageAdaptive;
+
+/** Offset 0x0332 - Core Turbo voltage Offset
+ The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
+**/
+ UINT16 CoreVoltageOffset;
+
+/** Offset 0x0334 - Core PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+ UINT8 CorePllVoltageOffset;
+
+/** Offset 0x0335 - Ring Downbin
+ Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
+ lower than the core ratio.0: Disable; <b>1: Enable.</b>
+ $EN_DIS
+**/
+ UINT8 RingDownBin;
+
+/** Offset 0x0336 - Ring voltage mode
+ Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
+ $EN_DIS
+**/
+ UINT8 RingVoltageMode;
+
+/** Offset 0x0337 - TjMax Offset
+ TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
+ TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
+**/
+ UINT8 TjMaxOffset;
+
+/** Offset 0x0338 - Ring voltage override
+ The ring voltage override which is applied to the entire range of cpu ring frequencies.
+ Valid Range 0 to 2000
+**/
+ UINT16 RingVoltageOverride;
+
+/** Offset 0x033A - Ring Turbo voltage Adaptive
+ Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
+ Valid Range 0 to 2000
+**/
+ UINT16 RingVoltageAdaptive;
+
+/** Offset 0x033C - Ring Turbo voltage Offset
+ The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
+**/
+ UINT16 RingVoltageOffset;
+
+/** Offset 0x033E - Enable or Disable TME
+ Enable or Disable TME; <b>0: Disable<b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TmeEnable;
+
+/** Offset 0x033F - Enable CPU CrashLog
+ Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 CpuCrashLogEnable;
+
+/** Offset 0x0340 - Reserved
+**/
+ UINT8 Reserved15[8];
+
+/** Offset 0x0348 - CPU Run Control
+ Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
+ No Change</b>
+ 0:Disabled, 1:Enabled, 2:No Change
**/
- UINT8 Reserved21[31];
+ UINT8 DebugInterfaceEnable;
+
+/** Offset 0x0349 - CPU Run Control Lock
+ Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 DebugInterfaceLockEnable;
/** Offset 0x034A - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
@@ -646,9 +1228,21 @@ typedef struct {
**/
UINT8 BiosGuardToolsInterface;
-/** Offset 0x034C - Reserved
+/** Offset 0x034C - EnableSgx
+ Enable/Disable. 0: Disable, Enable/Disable SGX feature, 1: enable, 2: Software Control
+ 0: Disable, 1: Enable, 2: Software Control
**/
- UINT8 Reserved22[4];
+ UINT8 EnableSgx;
+
+/** Offset 0x034D - Txt
+ Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 Txt;
+
+/** Offset 0x034E - Reserved
+**/
+ UINT8 Reserved16[2];
/** Offset 0x0350 - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
@@ -660,9 +1254,10 @@ typedef struct {
**/
UINT32 SinitMemorySize;
-/** Offset 0x0358 - Reserved
+/** Offset 0x0358 - TxtDprMemoryBase
+ Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
**/
- UINT8 Reserved23[8];
+ UINT64 TxtDprMemoryBase;
/** Offset 0x0360 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
@@ -674,9 +1269,54 @@ typedef struct {
**/
UINT32 TxtDprMemorySize;
-/** Offset 0x0368 - Reserved
+/** Offset 0x0368 - BiosAcmBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT32 BiosAcmBase;
+
+/** Offset 0x036C - BiosAcmSize
+ Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
+**/
+ UINT32 BiosAcmSize;
+
+/** Offset 0x0370 - ApStartupBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT32 ApStartupBase;
+
+/** Offset 0x0374 - TgaSize
+ Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
+**/
+ UINT32 TgaSize;
+
+/** Offset 0x0378 - TxtLcpPdBase
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
+**/
+ UINT64 TxtLcpPdBase;
+
+/** Offset 0x0380 - TxtLcpPdSize
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
**/
- UINT8 Reserved24[87];
+ UINT64 TxtLcpPdSize;
+
+/** Offset 0x0388 - IsTPMPresence
+ IsTPMPresence default values
+**/
+ UINT8 IsTPMPresence;
+
+/** Offset 0x0389 - Reserved
+**/
+ UINT8 Reserved17[6];
+
+/** Offset 0x038F - Enable PCH HSIO PCIE Rx Set Ctle
+ Enable PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtleEnable[24];
+
+/** Offset 0x03A7 - PCH HSIO PCIE Rx Set Ctle Value
+ PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtle[24];
/** Offset 0x03BF - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
@@ -828,9 +1468,23 @@ typedef struct {
**/
UINT8 PchSataHsioTxGen3DeEmph[8];
-/** Offset 0x056F - Reserved
+/** Offset 0x056F - PCH LPC Enhance the port 8xh decoding
+ Original LPC only decodes one byte of port 80h.
+ $EN_DIS
+**/
+ UINT8 PchLpcEnhancePort8xhDecoding;
+
+/** Offset 0x0570 - PCH Port80 Route
+ Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
+ $EN_DIS
**/
- UINT8 Reserved25[3];
+ UINT8 PchPort80Route;
+
+/** Offset 0x0571 - Enable SMBus ARP support
+ Enable SMBus ARP support.
+ $EN_DIS
+**/
+ UINT8 SmbusArpEnable;
/** Offset 0x0572 - Number of RsvdSmbusAddressTable.
The number of elements in the RsvdSmbusAddressTable.
@@ -839,7 +1493,18 @@ typedef struct {
/** Offset 0x0573 - Reserved
**/
- UINT8 Reserved26[4];
+ UINT8 Reserved18;
+
+/** Offset 0x0574 - SMBUS Base Address
+ SMBUS Base Address (IO space).
+**/
+ UINT16 PchSmbusIoBase;
+
+/** Offset 0x0576 - Enable SMBus Alert Pin
+ Enable SMBus Alert Pin.
+ $EN_DIS
+**/
+ UINT8 PchSmbAlertEnable;
/** Offset 0x0577 - Usage type for ClkSrc
0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
@@ -854,7 +1519,7 @@ typedef struct {
/** Offset 0x0597 - Reserved
**/
- UINT8 Reserved27[5];
+ UINT8 Reserved19[5];
/** Offset 0x059C - Enable PCIE RP Mask
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
@@ -875,9 +1540,43 @@ typedef struct {
**/
UINT8 SerialIoUartDebugControllerNumber;
-/** Offset 0x05A2 - Reserved
+/** Offset 0x05A2 - Serial Io Uart Debug Auto Flow
+ Enables UART hardware flow control, CTS and RTS lines.
+ $EN_DIS
+**/
+ UINT8 SerialIoUartDebugAutoFlow;
+
+/** Offset 0x05A3 - Reserved
+**/
+ UINT8 Reserved20;
+
+/** Offset 0x05A4 - Serial Io Uart Debug BaudRate
+ Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
+ 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
**/
- UINT8 Reserved28[14];
+ UINT32 SerialIoUartDebugBaudRate;
+
+/** Offset 0x05A8 - Serial Io Uart Debug Parity
+ Set default Parity.
+ 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 SerialIoUartDebugParity;
+
+/** Offset 0x05A9 - Serial Io Uart Debug Stop Bits
+ Set default stop bits.
+ 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+ UINT8 SerialIoUartDebugStopBits;
+
+/** Offset 0x05AA - Serial Io Uart Debug Data Bits
+ Set default word length. 0: Default, 5,6,7,8
+ 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
+**/
+ UINT8 SerialIoUartDebugDataBits;
+
+/** Offset 0x05AB - Reserved
+**/
+ UINT8 Reserved21[5];
/** Offset 0x05B0 - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
@@ -885,9 +1584,25 @@ typedef struct {
**/
UINT8 PcdIsaSerialUartBase;
-/** Offset 0x05B1 - Reserved
+/** Offset 0x05B1 - GT PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
**/
- UINT8 Reserved29[4];
+ UINT8 GtPllVoltageOffset;
+
+/** Offset 0x05B2 - Ring PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+ UINT8 RingPllVoltageOffset;
+
+/** Offset 0x05B3 - System Agent PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+ UINT8 SaPllVoltageOffset;
+
+/** Offset 0x05B4 - Memory Controller PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-63
+**/
+ UINT8 McPllVoltageOffset;
/** Offset 0x05B5 - MRC Safe Config
Enables/Disable MRC Safe Config
@@ -943,9 +1658,18 @@ typedef struct {
**/
UINT8 TcssDma1En;
-/** Offset 0x05BE - Reserved
+/** Offset 0x05BE - PcdSerialDebugBaudRate
+ Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
+ 3:9600, 4:19200, 6:56700, 7:115200
**/
- UINT8 Reserved30[2];
+ UINT8 PcdSerialDebugBaudRate;
+
+/** Offset 0x05BF - HobBufferSize
+ Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
+ total HOB size).
+ 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
+**/
+ UINT8 HobBufferSize;
/** Offset 0x05C0 - Early Command Training
Enables/Disable Early Command Training
@@ -953,9 +1677,324 @@ typedef struct {
**/
UINT8 ECT;
-/** Offset 0x05C1 - Reserved
+/** Offset 0x05C1 - SenseAmp Offset Training
+ Enables/Disable SenseAmp Offset Training
+ $EN_DIS
+**/
+ UINT8 SOT;
+
+/** Offset 0x05C2 - Early ReadMPR Timing Centering 2D
+ Enables/Disable Early ReadMPR Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDMPRTC2D;
+
+/** Offset 0x05C3 - Read MPR Training
+ Enables/Disable Read MPR Training
+ $EN_DIS
+**/
+ UINT8 RDMPRT;
+
+/** Offset 0x05C4 - Receive Enable Training
+ Enables/Disable Receive Enable Training
+ $EN_DIS
**/
- UINT8 Reserved31[102];
+ UINT8 RCVET;
+
+/** Offset 0x05C5 - Jedec Write Leveling
+ Enables/Disable Jedec Write Leveling
+ $EN_DIS
+**/
+ UINT8 JWRL;
+
+/** Offset 0x05C6 - Early Write Time Centering 2D
+ Enables/Disable Early Write Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 EWRTC2D;
+
+/** Offset 0x05C7 - Early Read Time Centering 2D
+ Enables/Disable Early Read Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDTC2D;
+
+/** Offset 0x05C8 - Write Timing Centering 1D
+ Enables/Disable Write Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRTC1D;
+
+/** Offset 0x05C9 - Write Voltage Centering 1D
+ Enables/Disable Write Voltage Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRVC1D;
+
+/** Offset 0x05CA - Read Timing Centering 1D
+ Enables/Disable Read Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 RDTC1D;
+
+/** Offset 0x05CB - Dimm ODT Training
+ Enables/Disable Dimm ODT Training
+ $EN_DIS
+**/
+ UINT8 DIMMODTT;
+
+/** Offset 0x05CC - DIMM RON Training
+ Enables/Disable DIMM RON Training
+ $EN_DIS
+**/
+ UINT8 DIMMRONT;
+
+/** Offset 0x05CD - Write Drive Strength/Equalization 2D
+ Enables/Disable Write Drive Strength/Equalization 2D
+ $EN_DIS
+**/
+ UINT8 WRDSEQT;
+
+/** Offset 0x05CE - Write Slew Rate Training
+ Enables/Disable Write Slew Rate Training
+ $EN_DIS
+**/
+ UINT8 WRSRT;
+
+/** Offset 0x05CF - Read ODT Training
+ Enables/Disable Read ODT Training
+ $EN_DIS
+**/
+ UINT8 RDODTT;
+
+/** Offset 0x05D0 - Read Equalization Training
+ Enables/Disable Read Equalization Training
+ $EN_DIS
+**/
+ UINT8 RDEQT;
+
+/** Offset 0x05D1 - Read Amplifier Training
+ Enables/Disable Read Amplifier Training
+ $EN_DIS
+**/
+ UINT8 RDAPT;
+
+/** Offset 0x05D2 - Write Timing Centering 2D
+ Enables/Disable Write Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRTC2D;
+
+/** Offset 0x05D3 - Read Timing Centering 2D
+ Enables/Disable Read Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDTC2D;
+
+/** Offset 0x05D4 - Write Voltage Centering 2D
+ Enables/Disable Write Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRVC2D;
+
+/** Offset 0x05D5 - Read Voltage Centering 2D
+ Enables/Disable Read Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDVC2D;
+
+/** Offset 0x05D6 - Command Voltage Centering
+ Enables/Disable Command Voltage Centering
+ $EN_DIS
+**/
+ UINT8 CMDVC;
+
+/** Offset 0x05D7 - Late Command Training
+ Enables/Disable Late Command Training
+ $EN_DIS
+**/
+ UINT8 LCT;
+
+/** Offset 0x05D8 - Round Trip Latency Training
+ Enables/Disable Round Trip Latency Training
+ $EN_DIS
+**/
+ UINT8 RTL;
+
+/** Offset 0x05D9 - Turn Around Timing Training
+ Enables/Disable Turn Around Timing Training
+ $EN_DIS
+**/
+ UINT8 TAT;
+
+/** Offset 0x05DA - Memory Test
+ Enables/Disable Memory Test
+ $EN_DIS
+**/
+ UINT8 MEMTST;
+
+/** Offset 0x05DB - DIMM SPD Alias Test
+ Enables/Disable DIMM SPD Alias Test
+ $EN_DIS
+**/
+ UINT8 ALIASCHK;
+
+/** Offset 0x05DC - Receive Enable Centering 1D
+ Enables/Disable Receive Enable Centering 1D
+ $EN_DIS
+**/
+ UINT8 RCVENC1D;
+
+/** Offset 0x05DD - Retrain Margin Check
+ Enables/Disable Retrain Margin Check
+ $EN_DIS
+**/
+ UINT8 RMC;
+
+/** Offset 0x05DE - Write Drive Strength Up/Dn independently
+ Enables/Disable Write Drive Strength Up/Dn independently
+ $EN_DIS
+**/
+ UINT8 WRDSUDT;
+
+/** Offset 0x05DF - ECC Support
+ Enables/Disable ECC Support
+ $EN_DIS
+**/
+ UINT8 EccSupport;
+
+/** Offset 0x05E0 - Reserved
+**/
+ UINT8 Reserved22[44];
+
+/** Offset 0x060C - Memory Remap
+ Enables/Disable Memory Remap
+ $EN_DIS
+**/
+ UINT8 RemapEnable;
+
+/** Offset 0x060D - Rank Interleave support
+ Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
+ the same time.
+ $EN_DIS
+**/
+ UINT8 RankInterleave;
+
+/** Offset 0x060E - Enhanced Interleave support
+ Enables/Disable Enhanced Interleave support
+ $EN_DIS
+**/
+ UINT8 EnhancedInterleave;
+
+/** Offset 0x060F - Ch Hash Support
+ Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
+ $EN_DIS
+**/
+ UINT8 ChHashEnable;
+
+/** Offset 0x0610 - Extern Therm Status
+ Enables/Disable Extern Therm Status
+ $EN_DIS
+**/
+ UINT8 EnableExtts;
+
+/** Offset 0x0611 - DDR PowerDown and idle counter
+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 EnablePwrDn;
+
+/** Offset 0x0612 - DDR PowerDown and idle counter
+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 EnablePwrDnLpddr;
+
+/** Offset 0x0613 - SelfRefresh Enable
+ Enables/Disable SelfRefresh Enable
+ $EN_DIS
+**/
+ UINT8 SrefCfgEna;
+
+/** Offset 0x0614 - Throttler CKEMin Defeature
+ Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 ThrtCkeMinDefeatLpddr;
+
+/** Offset 0x0615 - Throttler CKEMin Defeature
+ Enables/Disable Throttler CKEMin Defeature
+ $EN_DIS
+**/
+ UINT8 ThrtCkeMinDefeat;
+
+/** Offset 0x0616 - Enable RH Prevention
+ Enables/Disable RH Prevention
+ $EN_DIS
+**/
+ UINT8 RhPrevention;
+
+/** Offset 0x0617 - Exit On Failure (MRC)
+ Enables/Disable Exit On Failure (MRC)
+ $EN_DIS
+**/
+ UINT8 ExitOnFailure;
+
+/** Offset 0x0618 - Reserved
+**/
+ UINT8 Reserved23[2];
+
+/** Offset 0x061A - Duty Cycle Correction Training
+ Enable/Disable Duty Cycle Correction Training
+ $EN_DIS
+**/
+ UINT8 DCC;
+
+/** Offset 0x061B - Read Voltage Centering 1D
+ Enable/Disable Read Voltage Centering 1D
+ $EN_DIS
+**/
+ UINT8 RDVC1D;
+
+/** Offset 0x061C - TxDqTCO Comp Training
+ Enable/Disable TxDqTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 TXTCO;
+
+/** Offset 0x061D - ClkTCO Comp Training
+ Enable/Disable ClkTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 CLKTCO;
+
+/** Offset 0x061E - CMD Slew Rate Training
+ Enable/Disable CMD Slew Rate Training
+ $EN_DIS
+**/
+ UINT8 CMDSR;
+
+/** Offset 0x061F - CMD Drive Strength and Tx Equalization
+ Enable/Disable CMD Drive Strength and Tx Equalization
+ $EN_DIS
+**/
+ UINT8 CMDDSEQ;
+
+/** Offset 0x0620 - DIMM CA ODT Training
+ Enable/Disable DIMM CA ODT Training
+ $EN_DIS
+**/
+ UINT8 DIMMODTCA;
+
+/** Offset 0x0621 - TxDqsTCO Comp Training
+ Enable/Disable TxDqsTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 TXTCODQS;
+
+/** Offset 0x0622 - Reserved
+**/
+ UINT8 Reserved24[5];
/** Offset 0x0627 - Rank Margin Tool Per Bit
Enable/Disable Rank Margin Tool Per Bit
@@ -965,7 +2004,30 @@ typedef struct {
/** Offset 0x0628 - Reserved
**/
- UINT8 Reserved32[6];
+ UINT8 Reserved25[2];
+
+/** Offset 0x062A - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+ Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP
+ $EN_DIS
+**/
+ UINT8 Ddr4DdpSharedClock;
+
+/** Offset 0x062B - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ $EN_DIS
+**/
+ UINT8 Ddr4DdpSharedZq;
+
+/** Offset 0x062C - Ch Hash Interleaved Bit
+ Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
+ the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
+ 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+ UINT8 ChHashInterleaveBit;
+
+/** Offset 0x062D - Reserved
+**/
+ UINT8 Reserved26;
/** Offset 0x062E - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
@@ -973,9 +2035,106 @@ typedef struct {
**/
UINT16 ChHashMask;
-/** Offset 0x0630 - Reserved
+/** Offset 0x0630 - Base reference clock value
+ Base reference clock value, in Hertz(Default is 125Hz)
+ 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
+**/
+ UINT32 BClkFrequency;
+
+/** Offset 0x0634 - EPG DIMM Idd3N
+ Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
+ a per DIMM basis. Default is 26
+**/
+ UINT16 Idd3n;
+
+/** Offset 0x0636 - EPG DIMM Idd3P
+ Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
+ on a per DIMM basis. Default is 11
+**/
+ UINT16 Idd3p;
+
+/** Offset 0x0638 - RH Activation Probability
+ RH Activation Probability, Probability value is 1/2^(inputvalue)
+**/
+ UINT8 RhActProbability;
+
+/** Offset 0x0639 - Reserved
+**/
+ UINT8 Reserved27[40];
+
+/** Offset 0x0661 - Throttler CKEMin Timer
+ Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
+ Dfault is 0x00
+**/
+ UINT8 ThrtCkeMinTmr;
+
+/** Offset 0x0662 - Rapl Power Floor Ch0
+ Power budget ,range[255;0],(0= 5.3W Def)
+**/
+ UINT8 RaplPwrFlCh0;
+
+/** Offset 0x0663 - Rapl Power Floor Ch1
+ Power budget ,range[255;0],(0= 5.3W Def)
+**/
+ UINT8 RaplPwrFlCh1;
+
+/** Offset 0x0664 - Command Rate Support
+ CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
+ 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS
+**/
+ UINT8 EnCmdRate;
+
+/** Offset 0x0665 - REFRESH_2X_MODE
+ 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot
+ 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only
+**/
+ UINT8 Refresh2X;
+
+/** Offset 0x0666 - Energy Performance Gain
+ Enable/disable(default) Energy Performance Gain.
+ $EN_DIS
+**/
+ UINT8 EpgEnable;
+
+/** Offset 0x0667 - Row Hammer Solution
+ Type of method used to prevent Row Hammer. Default is Hardware RHP
+ 0:Hardware RHP, 1:2x Refresh
+**/
+ UINT8 RhSolution;
+
+/** Offset 0x0668 - User Manual Threshold
+ Disabled: Predefined threshold will be used.\n
+ Enabled: User Input will be used.
+ $EN_DIS
+**/
+ UINT8 UserThresholdEnable;
+
+/** Offset 0x0669 - User Manual Budget
+ Disabled: Configuration of memories will defined the Budget value.\n
+ Enabled: User Input will be used.
+ $EN_DIS
+**/
+ UINT8 UserBudgetEnable;
+
+/** Offset 0x066A - Reserved
**/
- UINT8 Reserved33[62];
+ UINT8 Reserved28;
+
+/** Offset 0x066B - Pwr Down Idle Timer
+ The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
+ AUTO: 64 for ULX/ULT, 128 for DT/Halo
+**/
+ UINT8 PwdwnIdleCounter;
+
+/** Offset 0x066C - Reserved
+**/
+ UINT8 Reserved29;
+
+/** Offset 0x066D - Bitmask of ranks that have CA bus terminated
+ Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
+ Rank0 is terminating and Rank1 is non-terminating</b>
+**/
+ UINT8 CmdRanksTerminated;
/** Offset 0x066E - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
@@ -986,9 +2145,17 @@ typedef struct {
**/
UINT8 PcdSerialDebugLevel;
-/** Offset 0x066F - Reserved
+/** Offset 0x066F - Fivr Faults
+ Fivr Faults; 0: Disabled; <b>1: Enabled.</b>
+ $EN_DIS
+**/
+ UINT8 FivrFaults;
+
+/** Offset 0x0670 - Fivr Efficiency
+ Fivr Efficiency Management; 0: Disabled; <b>1: Enabled.</b>
+ $EN_DIS
**/
- UINT8 Reserved34[2];
+ UINT8 FivrEfficiency;
/** Offset 0x0671 - Safe Mode Support
This option configures the varous items in the IO and MC to be more conservative.(def=Disable)
@@ -996,9 +2163,17 @@ typedef struct {
**/
UINT8 SafeMode;
-/** Offset 0x0672 - Reserved
+/** Offset 0x0672 - Ask MRC to clear memory content
+ Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
+ $EN_DIS
+**/
+ UINT8 CleanMemory;
+
+/** Offset 0x0673 - LpDdrDqDqsReTraining
+ Enables/Disable LpDdrDqDqsReTraining
+ $EN_DIS
**/
- UINT8 Reserved35[2];
+ UINT8 LpDdrDqDqsReTraining;
/** Offset 0x0674 - TCSS USB Port Enable
Bitmap for per port enabling
@@ -1007,7 +2182,66 @@ typedef struct {
/** Offset 0x0675 - Reserved
**/
- UINT8 Reserved36[71];
+ UINT8 Reserved30;
+
+/** Offset 0x0676 - Post Code Output Port
+ This option configures Post Code Output Port
+**/
+ UINT16 PostCodeOutputPort;
+
+/** Offset 0x0678 - RMTLoopCount
+ Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
+**/
+ UINT8 RMTLoopCount;
+
+/** Offset 0x0679 - Enable/Disable SA CRID
+ Enable: SA CRID, Disable (Default): SA CRID
+ $EN_DIS
+**/
+ UINT8 CridEnable;
+
+/** Offset 0x067A - Reserved
+**/
+ UINT8 Reserved31[18];
+
+/** Offset 0x068C - Size of PCIe IMR.
+ Size of PCIe IMR in megabytes
+**/
+ UINT16 PcieImrSize;
+
+/** Offset 0x068E - Enable PCIe IMR
+ 0: Disable(AUTO), 1: Enable
+ $EN_DIS
+**/
+ UINT8 PcieImrEnabled;
+
+/** Offset 0x068F - Reserved
+**/
+ UINT8 Reserved32[2];
+
+/** Offset 0x0691 - SerialDebugMrcLevel
+ MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 SerialDebugMrcLevel;
+
+/** Offset 0x0692 - Reserved
+**/
+ UINT8 Reserved33[32];
+
+/** Offset 0x06B2 - Ddr4OneDpc
+ DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
+ or on both (default)
+ 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
+**/
+ UINT8 Ddr4OneDpc;
+
+/** Offset 0x06B3 - Reserved
+**/
+ UINT8 Reserved34[9];
/** Offset 0x06BC - Command Pins Mirrored
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
@@ -1017,7 +2251,7 @@ typedef struct {
/** Offset 0x06C0 - Reserved
**/
- UINT8 Reserved37[5];
+ UINT8 Reserved35[5];
/** Offset 0x06C5 - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
@@ -1026,9 +2260,18 @@ typedef struct {
**/
UINT8 SkipExtGfxScan;
-/** Offset 0x06C6 - Reserved
+/** Offset 0x06C6 - Generate BIOS Data ACPI Table
+ Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
+ $EN_DIS
+**/
+ UINT8 BdatEnable;
+
+/** Offset 0x06C7 - Detect External Graphics device for LegacyOpROM
+ Detect and report if external graphics device only support LegacyOpROM or not (to
+ support CSM auto-enable). Enable(Default)=1, Disable=0
+ $EN_DIS
**/
- UINT8 Reserved38[2];
+ UINT8 ScanExtGfxForLegacyOpRom;
/** Offset 0x06C8 - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
@@ -1038,7 +2281,72 @@ typedef struct {
/** Offset 0x06C9 - Reserved
**/
- UINT8 Reserved39[122];
+ UINT8 Reserved36;
+
+/** Offset 0x06CA - Panel Power Enable
+ Control for enabling/disabling VDD force bit (Required only for early enabling of
+ eDP panel). 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 PanelPowerEnable;
+
+/** Offset 0x06CB - BdatTestType
+ Indicates the type of Memory Training data to populate into the BDAT ACPI table.
+ 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
+**/
+ UINT8 BdatTestType;
+
+/** Offset 0x06CC - Reserved
+**/
+ UINT8 Reserved37[98];
+
+/** Offset 0x072E - TotalFlashSize
+ Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
+**/
+ UINT16 TotalFlashSize;
+
+/** Offset 0x0730 - BiosSize
+ The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
+ 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
+ Range) so that a BIOS Update Script can be stored in the DPR.
+**/
+ UINT16 BiosSize;
+
+/** Offset 0x0732 - Reserved
+**/
+ UINT8 Reserved38[12];
+
+/** Offset 0x073E - Smbus dynamic power gating
+ Disable or Enable Smbus dynamic power gating.
+ $EN_DIS
+**/
+ UINT8 SmbusDynamicPowerGating;
+
+/** Offset 0x073F - Disable and Lock Watch Dog Register
+ Set 1 to clear WDT status, then disable and lock WDT registers.
+ $EN_DIS
+**/
+ UINT8 WdtDisableAndLock;
+
+/** Offset 0x0740 - SMBUS SPD Write Disable
+ Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
+ Disable bit. For security recommendations, SPD write disable bit must be set.
+ $EN_DIS
+**/
+ UINT8 SmbusSpdWriteDisable;
+
+/** Offset 0x0741 - VC Type
+ Virtual Channel Type Select: 0: VC0, 1: VC1.
+ 0: VC0, 1: VC1
+**/
+ UINT8 PchHdaVcType;
+
+/** Offset 0x0742 - Universal Audio Architecture compliance for DSP enabled system
+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+ driver or SST driver supported).
+ $EN_DIS
+**/
+ UINT8 PchHdaDspUaaCompliance;
/** Offset 0x0743 - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
@@ -1048,7 +2356,7 @@ typedef struct {
/** Offset 0x0744 - Reserved
**/
- UINT8 Reserved40[3];
+ UINT8 Reserved39[3];
/** Offset 0x0747 - Enable HD Audio DMIC_N Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
@@ -1057,7 +2365,7 @@ typedef struct {
/** Offset 0x0749 - Reserved
**/
- UINT8 Reserved41[3];
+ UINT8 Reserved40[3];
/** Offset 0x074C - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
@@ -1077,7 +2385,7 @@ typedef struct {
/** Offset 0x075D - Reserved
**/
- UINT8 Reserved42[3];
+ UINT8 Reserved41[3];
/** Offset 0x0760 - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
@@ -1112,9 +2420,53 @@ typedef struct {
**/
UINT8 PchHdaIDispCodecDisconnect;
-/** Offset 0x0775 - Reserved
+/** Offset 0x0775 - Force ME DID Init Status
+ Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
+ ME DID init stat value
+ $EN_DIS
+**/
+ UINT8 DidInitStat;
+
+/** Offset 0x0776 - CPU Replaced Polling Disable
+ Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
+ $EN_DIS
+**/
+ UINT8 DisableCpuReplacedPolling;
+
+/** Offset 0x0777 - ME DID Message
+ (DEPRECATED)Test, 0: disable, 1: enable, Enable/Disable ME DID Message (disable
+ will prevent the DID message from being sent)
+ $EN_DIS
+**/
+ UINT8 SendDidMsg;
+
+/** Offset 0x0778 - Check HECI message before send
+ Test, 0: disable, 1: enable, Enable/Disable message check.
+ $EN_DIS
+**/
+ UINT8 DisableMessageCheck;
+
+/** Offset 0x0779 - Skip MBP HOB
+ Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
+ $EN_DIS
+**/
+ UINT8 SkipMbpHob;
+
+/** Offset 0x077A - HECI2 Interface Communication
+ Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
+ $EN_DIS
+**/
+ UINT8 HeciCommunication2;
+
+/** Offset 0x077B - Enable KT device
+ Test, 0: disable, 1: enable, Enable or Disable KT device.
+ $EN_DIS
+**/
+ UINT8 KtDeviceEnable;
+
+/** Offset 0x077C - Reserved
**/
- UINT8 Reserved43[295];
+ UINT8 Reserved42[288];
/** Offset 0x089C - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
@@ -1124,7 +2476,7 @@ typedef struct {
/** Offset 0x089D - Reserved
**/
- UINT8 Reserved44;
+ UINT8 Reserved43;
/** Offset 0x089E - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
@@ -1135,7 +2487,7 @@ typedef struct {
/** Offset 0x089F - Reserved
**/
- UINT8 Reserved45[121];
+ UINT8 Reserved44[129];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -1154,11 +2506,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0918
+/** Offset 0x0920
**/
- UINT8 UnusedUpdSpace24[6];
+ UINT8 UnusedUpdSpace25[6];
-/** Offset 0x091E
+/** Offset 0x0926
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
index 46492de52c..c7086cd4a6 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspsUpd.h
@@ -85,9 +85,26 @@ typedef struct {
**/
typedef struct {
-/** Offset 0x0020 - Reserved
+/** Offset 0x0020 - Logo Pointer
+ Points to PEI Display Logo Image
**/
- UINT8 Reserved0[16];
+ UINT32 LogoPtr;
+
+/** Offset 0x0024 - Logo Size
+ Size of PEI Display Logo Image
+**/
+ UINT32 LogoSize;
+
+/** Offset 0x0028 - Blt Buffer Address
+ Address of Blt buffer
+**/
+ UINT32 BltBufferAddress;
+
+/** Offset 0x002C - Blt Buffer Size
+ Size of Blt Buffer, is equal to PixelWidth * PixelHeight * 4 bytes (the size of
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL)
+**/
+ UINT32 BltBufferSize;
/** Offset 0x0030 - Graphics Configuration Ptr
Points to VBT
@@ -100,9 +117,31 @@ typedef struct {
**/
UINT8 Device4Enable;
-/** Offset 0x0035 - Reserved
+/** Offset 0x0035 - Show SPI controller
+ Enable/disable to show SPI controller.
+ $EN_DIS
+**/
+ UINT8 ShowSpiController;
+
+/** Offset 0x0036 - Reserved
+**/
+ UINT8 Reserved0[2];
+
+/** Offset 0x0038 - MicrocodeRegionBase
+ Memory Base of Microcode Updates
+**/
+ UINT32 MicrocodeRegionBase;
+
+/** Offset 0x003C - MicrocodeRegionSize
+ Size of Microcode Updates
+**/
+ UINT32 MicrocodeRegionSize;
+
+/** Offset 0x0040 - Turbo Mode
+ Enable/Disable Turbo mode. 0: disable, 1: enable
+ $EN_DIS
**/
- UINT8 Reserved1[12];
+ UINT8 TurboMode;
/** Offset 0x0041 - Enable SATA SALP Support
Enable/disable SATA Aggressive Link Power Management.
@@ -142,7 +181,65 @@ typedef struct {
/** Offset 0x006D - Reserved
**/
- UINT8 Reserved2[28];
+ UINT8 Reserved1[3];
+
+/** Offset 0x0070 - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+ The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
+**/
+ UINT32 DevIntConfigPtr;
+
+/** Offset 0x0074 - Number of DevIntConfig Entry
+ Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
+ must not be NULL.
+**/
+ UINT8 NumOfDevIntConfig;
+
+/** Offset 0x0075 - PIRQx to IRQx Map Config
+ PIRQx to IRQx mapping. The valid value is 0x00 to 0x0F for each. First byte is for
+ PIRQA, second byte is for PIRQB, and so on. The setting is only available in Legacy
+ 8259 PCI mode.
+**/
+ UINT8 PxRcConfig[8];
+
+/** Offset 0x007D - Select GPIO IRQ Route
+ GPIO IRQ Select. The valid value is 14 or 15.
+**/
+ UINT8 GpioIrqRoute;
+
+/** Offset 0x007E - Select SciIrqSelect
+ SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
+**/
+ UINT8 SciIrqSelect;
+
+/** Offset 0x007F - Select TcoIrqSelect
+ TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
+**/
+ UINT8 TcoIrqSelect;
+
+/** Offset 0x0080 - Enable/Disable Tco IRQ
+ Enable/disable TCO IRQ
+ $EN_DIS
+**/
+ UINT8 TcoIrqEnable;
+
+/** Offset 0x0081 - PCH HDA Verb Table Entry Number
+ Number of Entries in Verb Table.
+**/
+ UINT8 PchHdaVerbTableEntryNum;
+
+/** Offset 0x0082 - Reserved
+**/
+ UINT8 Reserved2[2];
+
+/** Offset 0x0084 - PCH HDA Verb Table Pointer
+ Pointer to Array of pointers to Verb Table.
+**/
+ UINT32 PchHdaVerbTablePtr;
+
+/** Offset 0x0088 - PCH HDA Codec Sx Wake Capability
+ Capability to detect wake initiated by a codec in Sx
+**/
+ UINT8 PchHdaCodecSxWakeCapability;
/** Offset 0x0089 - Enable SATA
Enable/disable SATA controller.
@@ -162,9 +259,21 @@ typedef struct {
**/
UINT8 SerialIoSpiMode[7];
-/** Offset 0x0092 - Reserved
+/** Offset 0x0092 - SPI<N> Chip Select Polarity
+ Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
+ 1:SerialIoSpiCsActiveHigh
**/
- UINT8 Reserved3[35];
+ UINT8 SerialIoSpiCsPolarity[14];
+
+/** Offset 0x00A0 - Reserved
+**/
+ UINT8 Reserved3[14];
+
+/** Offset 0x00AE - SPIn Default Chip Select Output
+ Sets Default CS as Output. N represents controller index: SPI0, SPI1, ... Available
+ options: 0:CS0, 1:CS1
+**/
+ UINT8 SerialIoSpiDefaultCsOutput[7];
/** Offset 0x00B5 - SPIn Default Chip Select Mode HW/SW
Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
@@ -187,7 +296,38 @@ typedef struct {
/** Offset 0x00CA - Reserved
**/
- UINT8 Reserved4[65];
+ UINT8 Reserved4[2];
+
+/** Offset 0x00CC - Default BaudRate for each Serial IO UART
+ Set default BaudRate Supported from 0 - default to 6000000
+**/
+ UINT32 SerialIoUartBaudRate[7];
+
+/** Offset 0x00E8 - Default ParityType for each Serial IO UART
+ Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 SerialIoUartParity[7];
+
+/** Offset 0x00EF - Default DataBits for each Serial IO UART
+ Set default word length. 0: Default, 5,6,7,8
+**/
+ UINT8 SerialIoUartDataBits[7];
+
+/** Offset 0x00F6 - Default StopBits for each Serial IO UART
+ Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
+ TwoStopBits
+**/
+ UINT8 SerialIoUartStopBits[7];
+
+/** Offset 0x00FD - Power Gating mode for each Serial IO UART that works in COM mode
+ Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
+**/
+ UINT8 SerialIoUartPowerGating[7];
+
+/** Offset 0x0104 - Enable Dma for each Serial IO UART that supports it
+ Set DMA/PIO mode. 0: Disabled, 1: Enabled
+**/
+ UINT8 SerialIoUartDmaEnable[7];
/** Offset 0x010B - Enables UART hardware flow control, CTS and RTS lines
Enables UART hardware flow control, CTS and RTS lines.
@@ -230,9 +370,11 @@ typedef struct {
**/
UINT8 SerialIoDebugUartNumber;
-/** Offset 0x0185 - Reserved
+/** Offset 0x0185 - Serial IO UART DBG2 table
+ Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b>
+ 1: Enable.
**/
- UINT8 Reserved6[7];
+ UINT8 SerialIoUartDbg2[7];
/** Offset 0x018C - I2Cn Device Mode
Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
@@ -252,9 +394,16 @@ typedef struct {
**/
UINT32 PchSerialIoI2cSclPinMux[8];
-/** Offset 0x01D4 - Reserved
+/** Offset 0x01D4 - PCH SerialIo I2C Pads Termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
+ respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
+**/
+ UINT8 PchSerialIoI2cPadsTermination[8];
+
+/** Offset 0x01DC - Reserved
**/
- UINT8 Reserved7[192];
+ UINT8 Reserved6[184];
/** Offset 0x0294 - USB Per Port HS Preemphasis Bias
USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
@@ -304,9 +453,37 @@ typedef struct {
**/
UINT8 Usb3HsioTxDownscaleAmp[10];
-/** Offset 0x02FC - Reserved
+/** Offset 0x02FC
+**/
+ UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];
+
+/** Offset 0x0306
+**/
+ UINT8 PchUsb3HsioFilterSelNEnable[10];
+
+/** Offset 0x0310
**/
- UINT8 Reserved8[80];
+ UINT8 PchUsb3HsioFilterSelPEnable[10];
+
+/** Offset 0x031A
+**/
+ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];
+
+/** Offset 0x0324
+**/
+ UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10];
+
+/** Offset 0x032E
+**/
+ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10];
+
+/** Offset 0x0338
+**/
+ UINT8 PchUsb3HsioFilterSelN[10];
+
+/** Offset 0x0342
+**/
+ UINT8 PchUsb3HsioFilterSelP[10];
/** Offset 0x034C - Enable LAN
Enable/disable LAN controller.
@@ -316,7 +493,7 @@ typedef struct {
/** Offset 0x034D - Reserved
**/
- UINT8 Reserved9[11];
+ UINT8 Reserved7[11];
/** Offset 0x0358 - PCIe PTM enable/disable
Enable/disable Precision Time Measurement for PCIE Root Ports.
@@ -325,7 +502,36 @@ typedef struct {
/** Offset 0x0370 - Reserved
**/
- UINT8 Reserved10[58];
+ UINT8 Reserved8[48];
+
+/** Offset 0x03A0 - USB PDO Programming
+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
+ during later phase. 1: enable, 0: disable
+ $EN_DIS
+**/
+ UINT8 UsbPdoProgramming;
+
+/** Offset 0x03A1 - Reserved
+**/
+ UINT8 Reserved9[3];
+
+/** Offset 0x03A4 - Power button debounce configuration
+ Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
+ be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
+**/
+ UINT32 PmcPowerButtonDebounce;
+
+/** Offset 0x03A8 - PCH eSPI Master and Slave BME enabled
+ PCH eSPI Master and Slave BME enabled
+ $EN_DIS
+**/
+ UINT8 PchEspiBmeMasterSlaveEnabled;
+
+/** Offset 0x03A9 - PCH SATA use RST Legacy OROM
+ Use PCH SATA RST Legacy OROM when CSM is Enabled
+ $EN_DIS
+**/
+ UINT8 SataRstLegacyOrom;
/** Offset 0x03AA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
@@ -337,9 +543,15 @@ typedef struct {
**/
UINT8 PchFivrExtV1p05RailSupportedVoltageStates;
-/** Offset 0x03AC - Reserved
+/** Offset 0x03AC - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+ Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
**/
- UINT8 Reserved11[3];
+ UINT16 PchFivrExtV1p05RailVoltage;
+
+/** Offset 0x03AE - External V1P05 Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtV1p05RailIccMax;
/** Offset 0x03AF - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
@@ -353,7 +565,23 @@ typedef struct {
/** Offset 0x03B1 - Reserved
**/
- UINT8 Reserved12[5];
+ UINT8 Reserved10;
+
+/** Offset 0x03B2 - External Vnn Voltage Value that will be used in S0ix/Sx states
+ Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
+**/
+ UINT16 PchFivrExtVnnRailVoltage;
+
+/** Offset 0x03B4 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+ Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtVnnRailIccMax;
+
+/** Offset 0x03B5 - Mask to enable the usage of external Vnn VR rail in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
+ Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtVnnRailSxEnabledStates;
/** Offset 0x03B6 - External Vnn Voltage Value that will be used in Sx states
Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
@@ -361,9 +589,11 @@ typedef struct {
**/
UINT16 PchFivrExtVnnRailSxVoltage;
-/** Offset 0x03B8 - Reserved
+/** Offset 0x03B8 - External Vnn Icc Max Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
+ is 1mA and maximal possible value is 200mA
**/
- UINT8 Reserved13;
+ UINT8 PchFivrExtVnnRailSxIccMax;
/** Offset 0x03B9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
@@ -377,9 +607,11 @@ typedef struct {
**/
UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
-/** Offset 0x03BB - Reserved
+/** Offset 0x03BB - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to retention mode voltage.
**/
- UINT8 Reserved14;
+ UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime;
/** Offset 0x03BC - Transition time in microseconds from Off (0V) to High Current Mode Voltage
This field has 1us resolution. When value is 0 Transition to 0V is disabled.
@@ -388,7 +620,45 @@ typedef struct {
/** Offset 0x03BE - Reserved
**/
- UINT8 Reserved15[20];
+ UINT8 Reserved11[2];
+
+/** Offset 0x03C0 - Trace Hub Memory Base
+ If Trace Hub is enabled and trace to memory is desired, BootLoader needs to allocate
+ trace hub memory as reserved and uncacheable, set the base to ensure Trace Hub
+ memory is configured properly.
+**/
+ UINT32 TraceHubMemBase;
+
+/** Offset 0x03C4 - PMC Debug Message Enable
+ When Enabled, PMC HW will send debug messages to trace hub; When Disabled, PMC HW
+ will never send debug meesages to trace hub. Noted: When Enabled, may not enter S0ix
+ $EN_DIS
+**/
+ UINT8 PmcDbgMsgEn;
+
+/** Offset 0x03C5 - Reserved
+**/
+ UINT8 Reserved12[3];
+
+/** Offset 0x03C8 - Pointer of ChipsetInit Binary
+ ChipsetInit Binary Pointer.
+**/
+ UINT32 ChipsetInitBinPtr;
+
+/** Offset 0x03CC - Length of ChipsetInit Binary
+ ChipsetInit Binary Length.
+**/
+ UINT32 ChipsetInitBinLen;
+
+/** Offset 0x03D0 - FIVR Dynamic Power Management
+ Enable/Disable FIVR Dynamic Power Management.
+ $EN_DIS
+**/
+ UINT8 PchFivrDynPm;
+
+/** Offset 0x03D1 - Reserved
+**/
+ UINT8 Reserved13;
/** Offset 0x03D2 - External V1P05 Icc Max Value
Granularity of this setting is 1mA and maximal possible value is 500mA
@@ -397,7 +667,7 @@ typedef struct {
/** Offset 0x03D4 - Reserved
**/
- UINT8 Reserved16[16];
+ UINT8 Reserved14[16];
/** Offset 0x03E4 - CNVi Configuration
This option allows for automatic detection of Connectivity Solution. [Auto Detection]
@@ -420,7 +690,7 @@ typedef struct {
/** Offset 0x03E7 - Reserved
**/
- UINT8 Reserved17;
+ UINT8 Reserved15;
/** Offset 0x03E8 - CNVi RF_RESET pin muxing
Select CNVi RF_RESET# pin depending on board routing. TGP-LP: GPP_A8 = 0x2942E408(default)
@@ -435,9 +705,42 @@ typedef struct {
**/
UINT32 CnviClkreqPinMux;
-/** Offset 0x03F0 - Reserved
+/** Offset 0x03F0 - Enable Host C10 reporting through eSPI
+ Enable/disable Host C10 reporting to Slave via eSPI Virtual Wire.
+ $EN_DIS
**/
- UINT8 Reserved18[14];
+ UINT8 PchEspiHostC10ReportEnable;
+
+/** Offset 0x03F1 - PCH USB2 PHY Power Gating enable
+ 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
+ Sus Well PG
+ $EN_DIS
+**/
+ UINT8 PmcUsb2PhySusPgEnable;
+
+/** Offset 0x03F2 - PCH USB OverCurrent mapping enable
+ 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
+ mapping allow for NOA usage of OC pins
+ $EN_DIS
+**/
+ UINT8 PchUsbOverCurrentEnable;
+
+/** Offset 0x03F3 - Espi Lgmr Memory Range decode
+ This option enables or disables espi lgmr
+ $EN_DIS
+**/
+ UINT8 PchEspiLgmrEnable;
+
+/** Offset 0x03F4 - Reserved
+**/
+ UINT8 Reserved16[2];
+
+/** Offset 0x03F6 - Set SATA DEVSLP GPIO Reset Config
+ Set SATA DEVSLP GPIO Reset Config per port. 0x00 - GpioResetDefault, 0x01 - GpioResumeReset,
+ 0x03 - GpioHostDeepReset, 0x05 - GpioPlatformReset, 0x07 - GpioDswReset. One byte
+ for each port, byte0 for port0, byte1 for port1, and so on.
+**/
+ UINT8 SataPortsDevSlpResetConfig[8];
/** Offset 0x03FE - HECI3 state
The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
@@ -446,15 +749,140 @@ typedef struct {
**/
UINT8 Heci3Enabled;
-/** Offset 0x03FF - Reserved
+/** Offset 0x03FF - PCHHOT# pin
+ Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchHotEnable;
+
+/** Offset 0x0400 - SATA LED
+ SATA LED indicating SATA controller activity. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 SataLedEnable;
+
+/** Offset 0x0401 - VRAlert# Pin
+ When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
+ to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchPmVrAlert;
+
+/** Offset 0x0402 - AMT Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
+ $EN_DIS
+**/
+ UINT8 AmtEnabled;
+
+/** Offset 0x0403 - WatchDog Timer Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
+ is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 WatchDogEnabled;
+
+/** Offset 0x0404 - Manageability Mode set by Mebx
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable Manageability Mode.
+ $EN_DIS
+**/
+ UINT8 ManageabilityMode;
+
+/** Offset 0x0405 - PET Progress
+ Enable/Disable. 0: Disable, 1: enable, Enable/Disable PET Events Progress to receive
+ PET Events. Setting is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 FwProgress;
+
+/** Offset 0x0406 - SOL Switch
+ Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
+ Setting is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 AmtSolEnabled;
+
+/** Offset 0x0407 - Reserved
+**/
+ UINT8 Reserved17;
+
+/** Offset 0x0408 - OS Timer
+ 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+ UINT16 WatchDogTimerOs;
+
+/** Offset 0x040A - BIOS Timer
+ 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+ UINT16 WatchDogTimerBios;
+
+/** Offset 0x040C - Remote Assistance Trigger Availablilty
+ Enable/Disable. 0: Disable, 1: enable, Remote Assistance enable/disable state by Mebx.
+ $EN_DIS
+**/
+ UINT8 RemoteAssistance;
+
+/** Offset 0x040D - KVM Switch
+ Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx. Setting
+ is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 AmtKvmEnabled;
+
+/** Offset 0x040E - KVM Switch
+ Enable/Disable. 0: Disable, 1: enable, KVM enable/disable state by Mebx.
+ $EN_DIS
+**/
+ UINT8 ForcMebxSyncUp;
+
+/** Offset 0x040F - PCH PCIe root port connection type
+ 0: built-in device, 1:slot
+**/
+ UINT8 PcieRpSlotImplemented[24];
+
+/** Offset 0x0427 - PCIE RP Access Control Services Extended Capability
+ Enable/Disable PCIE RP Access Control Services Extended Capability
+**/
+ UINT8 PcieRpAcsEnabled[24];
+
+/** Offset 0x043F - PCIE RP Clock Power Management
+ Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
+ can still be controlled by L1 PM substates mechanism
+**/
+ UINT8 PcieRpEnableCpm[24];
+
+/** Offset 0x0457 - Reserved
+**/
+ UINT8 Reserved18;
+
+/** Offset 0x0458 - PCIE RP Detect Timeout Ms
+ The number of milliseconds within 0~65535 in reference code will wait for link to
+ exit Detect state for enabled ports before assuming there is no device and potentially
+ disabling the port.
+**/
+ UINT16 PcieRpDetectTimeoutMs[24];
+
+/** Offset 0x0488 - ModPHY SUS Power Domain Dynamic Gating
+ Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
+ PCH-H. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcModPhySusPgEnable;
+
+/** Offset 0x0489 - Reserved
+**/
+ UINT8 Reserved19[2];
+
+/** Offset 0x048B - Enable/Disable PavpEnable
+ Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
+ $EN_DIS
**/
- UINT8 Reserved19[141];
+ UINT8 PavpEnable;
/** Offset 0x048C - CdClock Frequency selection
0 (Default) Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2:
- 312 Mhz, 3: 552 Mhz, 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz
+ 312 Mhz, 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
0xFF: Auto (Max based on reference clock frequency), 0: 192, 1: 307.2, 2: 312 Mhz,
- 3: 552 Mhz, 4: 556.8 Mhz, 5: 648 Mhz, 6: 652.8 Mhz
+ 3: 324Mhz, 4: 326.4 Mhz, 5: 552 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz
**/
UINT8 CdClock;
@@ -471,9 +899,11 @@ typedef struct {
**/
UINT8 D3HotEnable;
-/** Offset 0x048F - Reserved
+/** Offset 0x048F - Enable or disable GNA device
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
**/
- UINT8 Reserved20;
+ UINT8 GnaEnable;
/** Offset 0x0490 - TypeC port GPIO setting
GPIO Ping number for Type C Aux Oritation setting, use the GpioPad that is defined
@@ -482,9 +912,10 @@ typedef struct {
**/
UINT32 IomTypeCPortPadCfg[8];
-/** Offset 0x04B0 - Reserved
+/** Offset 0x04B0 - CPU USB3 Port Over Current Pin
+ Describe the specific over current pin number of USBC Port N.
**/
- UINT8 Reserved21[8];
+ UINT8 CpuUsb3OverCurrentPin[8];
/** Offset 0x04B8 - Enable D3 Cold in TCSS
This policy will enable/disable D3 cold support in IOM
@@ -494,7 +925,7 @@ typedef struct {
/** Offset 0x04B9 - Reserved
**/
- UINT8 Reserved22[8];
+ UINT8 Reserved20[8];
/** Offset 0x04C1 - Enable VMD controller
Enable/disable to VMD controller.0: Disable(Default); 1: Enable
@@ -502,9 +933,69 @@ typedef struct {
**/
UINT8 VmdEnable;
-/** Offset 0x04C2 - Reserved
+/** Offset 0x04C2 - Enable VMD portA Support
+ Enable/disable to VMD portA Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortA;
+
+/** Offset 0x04C3 - Enable VMD portB Support
+ Enable/disable to VMD portB Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortB;
+
+/** Offset 0x04C4 - Enable VMD portC Support
+ Enable/disable to VMD portC Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortC;
+
+/** Offset 0x04C5 - Enable VMD portD Support
+ Enable/disable to VMD portD Support.
+ $EN_DIS
+**/
+ UINT8 VmdPortD;
+
+/** Offset 0x04C6 - Reserved
+**/
+ UINT8 Reserved21;
+
+/** Offset 0x04C7 - VMD Config Bar Attributes
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH(Default)
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
**/
- UINT8 Reserved23[12];
+ UINT8 VmdCfgBarAttr;
+
+/** Offset 0x04C8 - Reserved
+**/
+ UINT8 Reserved22;
+
+/** Offset 0x04C9 - VMD Mem Bar1 Attributes
+ 0: VMD_32BIT_NONPREFETCH(Default), 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+**/
+ UINT8 VmdMemBar1Attr;
+
+/** Offset 0x04CA - Reserved
+**/
+ UINT8 Reserved23;
+
+/** Offset 0x04CB - VMD Mem Bar2 Attributes
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH(Default), 2: VMD_64BIT_PREFETCH
+ 0: VMD_32BIT_NONPREFETCH, 1: VMD_64BIT_NONPREFETCH, 2: VMD_64BIT_PREFETCH
+**/
+ UINT8 VmdMemBar2Attr;
+
+/** Offset 0x04CC - Enable/Disable PMC-PD Solution
+ This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
+ $EN_DIS
+**/
+ UINT8 PmcPdEnable;
+
+/** Offset 0x04CD - Reserved
+**/
+ UINT8 Reserved24;
/** Offset 0x04CE - TCSS Aux Orientation Override Enable
Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
@@ -516,9 +1007,16 @@ typedef struct {
**/
UINT16 TcssHslOri;
-/** Offset 0x04D2 - Reserved
+/** Offset 0x04D2 - USB override in IOM
+ This policy will enable/disable USB Connect override in IOM
+ $EN_DIS
+**/
+ UINT8 UsbOverride;
+
+/** Offset 0x04D3 - TCSS USB Port Enable
+ Bits 0, 1, ... max Type C port control enables
**/
- UINT8 Reserved24[2];
+ UINT8 UsbTcPortEn;
/** Offset 0x04D4 - ITBT Root Port Enable
ITBT Root Port Enable, 0:Disable, 1:Enable
@@ -526,9 +1024,11 @@ typedef struct {
**/
UINT8 ITbtPcieRootPortEn[4];
-/** Offset 0x04D8 - Reserved
+/** Offset 0x04D8 - ITBTForcePowerOn Timeout value
+ ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
+ 100 = 100 ms.
**/
- UINT8 Reserved25[2];
+ UINT16 ITbtForcePowerOnTimeoutInMs;
/** Offset 0x04DA - ITbtConnectTopology Timeout value
ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
@@ -536,9 +1036,26 @@ typedef struct {
**/
UINT16 ITbtConnectTopologyTimeoutInMs;
-/** Offset 0x04DC - Reserved
+/** Offset 0x04DC - VCCST request for IOM
+ This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
+ $EN_DIS
+**/
+ UINT8 VccSt;
+
+/** Offset 0x04DD - Reserved
**/
- UINT8 Reserved26[7];
+ UINT8 Reserved25;
+
+/** Offset 0x04DE - ITBT DMA LTR
+ TCSS DMA1, DMA2 LTR value
+**/
+ UINT16 ITbtDmaLtr[2];
+
+/** Offset 0x04E2 - Enable/Disable CrashLog
+ Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog
+ $EN_DIS
+**/
+ UINT8 CpuCrashLogEnable;
/** Offset 0x04E3 - Enable/Disable PTM
This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
@@ -546,9 +1063,197 @@ typedef struct {
**/
UINT8 PtmEnabled[4];
-/** Offset 0x04E7 - Reserved
+/** Offset 0x04E7 - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 SaPcieItbtRpLtrEnable[4];
+
+/** Offset 0x04EB - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4];
+
+/** Offset 0x04EF - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x04F3 - Reserved
+**/
+ UINT8 Reserved26;
+
+/** Offset 0x04F4 - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4];
+
+/** Offset 0x04FC - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
+
+/** Offset 0x0500 - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
- UINT8 Reserved27[194];
+ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x0504 - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
+
+/** Offset 0x050C - Force LTR Override
+ Force LTR Override.
+**/
+ UINT8 SaPcieItbtRpForceLtrOverride[4];
+
+/** Offset 0x0510 - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 SaPcieItbtRpLtrConfigLock[4];
+
+/** Offset 0x0514 - Advanced Encryption Standard (AES) feature
+ Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
+ $EN_DIS
+**/
+ UINT8 AesEnable;
+
+/** Offset 0x0515 - Power State 3 enable/disable
+ PCODE MMIO Mailbox: Power State 3 enable/disable; 0: Disable; <b>1: Enable</b>.
+ For all VR Indexes
+**/
+ UINT8 Psi3Enable[5];
+
+/** Offset 0x051A - Power State 4 enable/disable
+ PCODE MMIO Mailbox: Power State 4 enable/disable; 0: Disable; <b>1: Enable</b>.For
+ all VR Indexes
+**/
+ UINT8 Psi4Enable[5];
+
+/** Offset 0x051F - Reserved
+**/
+ UINT8 Reserved27;
+
+/** Offset 0x0520 - Imon slope correction
+ PCODE MMIO Mailbox: Imon slope correction. Specified in 1/100 increment values.
+ Range is 0-200. 125 = 1.25. <b>0: Auto</b>.For all VR Indexes
+**/
+ UINT16 ImonSlope[5];
+
+/** Offset 0x052A - Imon offset correction
+ PCODE MMIO Mailbox: Imon offset correction. Value is a 2's complement signed integer.
+ Units 1/1000, Range 0-63999. For an offset = 12.580, use 12580. <b>0: Auto</b>
+**/
+ UINT16 ImonOffset[5];
+
+/** Offset 0x0534 - Enable/Disable BIOS configuration of VR
+ Enable/Disable BIOS configuration of VR; <b>0: Disable</b>; 1: Enable.For all VR Indexes
+**/
+ UINT8 VrConfigEnable[5];
+
+/** Offset 0x0539 - Thermal Design Current enable/disable
+ PCODE MMIO Mailbox: Thermal Design Current enable/disable; <b>0: Disable</b>; 1:
+ Enable.For all VR Indexes
+**/
+ UINT8 TdcEnable[5];
+
+/** Offset 0x053E - Thermal Design Current time window
+ PCODE MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.
+ DEPRECATED. Valid Values 1 - 1ms , 2 - 2ms , 3 - 3ms , 4 - 4ms , 5 - 5ms , 6 -
+ 6ms , 7 - 7ms , 8 - 8ms , 10 - 10ms.For all VR Index
+**/
+ UINT8 TdcTimeWindow[5];
+
+/** Offset 0x0543 - Thermal Design Current Lock
+ PCODE MMIO Mailbox: Thermal Design Current Lock; <b>0: Disable</b>; 1: Enable.For
+ all VR Indexes
+**/
+ UINT8 TdcLock[5];
+
+/** Offset 0x0548 - Platform Psys slope correction
+ PCODE MMIO Mailbox: Platform Psys slope correction. <b>0 - Auto</b> Specified in
+ 1/100 increment values. Range is 0-200. 125 = 1.25
+**/
+ UINT8 PsysSlope;
+
+/** Offset 0x0549
+**/
+ UINT8 PsysOffset;
+
+/** Offset 0x054A - Acoustic Noise Mitigation feature
+ Enable or Disable Acoustic Noise Mitigation feature. <b>0: Disabled</b>; 1: Enabled
+ $EN_DIS
+**/
+ UINT8 AcousticNoiseMitigation;
+
+/** Offset 0x054B - Reserved
+**/
+ UINT8 Reserved28[10];
+
+/** Offset 0x0555 - Enable multi phases silicon initial
+ A switch to determine MultiPhaseSiInit will be executed or not
+ $EN_DIS
+**/
+ UINT8 EnableMultiPhaseSiliconInit;
+
+/** Offset 0x0556 - Reserved
+**/
+ UINT8 Reserved29[10];
+
+/** Offset 0x0560 - AcLoadline
+ PCODE MMIO Mailbox: AcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+ 0-6249. <b>Intel Recommended Defaults vary by domain and SKU.
+**/
+ UINT16 AcLoadline[5];
+
+/** Offset 0x056A - DcLoadline
+ PCODE MMIO Mailbox: DcLoadline in 1/100 mOhms (ie. 1250 = 12.50 mOhm); Range is
+ 0-6249.<b>Intel Recommended Defaults vary by domain and SKU.</b>
+**/
+ UINT16 DcLoadline[5];
+
+/** Offset 0x0574 - Power State 1 Threshold current
+ PCODE MMIO Mailbox: Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi1Threshold[5];
+
+/** Offset 0x057E - Power State 2 Threshold current
+ PCODE MMIO Mailbox: Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi2Threshold[5];
+
+/** Offset 0x0588 - Power State 3 Threshold current
+ PCODE MMIO Mailbox: Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.
+**/
+ UINT16 Psi3Threshold[5];
+
+/** Offset 0x0592 - Icc Max limit
+ PCODE MMIO Mailbox: VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A
+**/
+ UINT16 IccMax[5];
+
+/** Offset 0x059C - VR Voltage Limit
+ PCODE MMIO Mailbox: VR Voltage Limit. DEPRECATED, Range is 0-7999mV.
+**/
+ UINT16 VrVoltageLimit[5];
+
+/** Offset 0x05A6 - Enable VR specific mailbox command
+ VR specific mailbox commands. <b>00b - no VR specific command sent.</b> 01b - A
+ VR mailbox command specifically for the MPS IMPV8 VR will be sent. 10b - VR specific
+ command sent for PS4 exit issue. 11b - Reserved.
+ $EN_DIS
+**/
+ UINT8 SendVrMbxCmd;
+
+/** Offset 0x05A7 - Reserved
+**/
+ UINT8 Reserved30;
+
+/** Offset 0x05A8 - Enable or Disable TXT
+ Enable or Disable TXT; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 TxtEnable;
/** Offset 0x05A9 - Skip Multi-Processor Initialization
When this is skipped, boot loader must initialize processors before SilicionInit
@@ -557,9 +1262,28 @@ typedef struct {
**/
UINT8 SkipMpInit;
-/** Offset 0x05AA - Reserved
+/** Offset 0x05AA - FIVR RFI Frequency
+ PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz. <b>0:
+ Auto</b>. Range varies based on XTAL clock: 0-1918 (Up to 191.8HMz) for 24MHz clock;
+ 0-1535 (Up to 153.5MHz) for 19MHz clock.
+**/
+ UINT16 FivrRfiFrequency;
+
+/** Offset 0x05AC - FIVR RFI Spread Spectrum
+ Set the Spread Spectrum Range. <b>1.5%</b>; Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%,
+ 6%. Each Range is translated to an encoded value for FIVR register. 0.5% = 0, 1%
+ = 3, 1.5% = 8, 2% = 18, 3% = 28, 4% = 34, 5% = 39, 6% = 44.
+**/
+ UINT8 FivrSpreadSpectrum;
+
+/** Offset 0x05AD - Reserved
+**/
+ UINT8 Reserved31[3];
+
+/** Offset 0x05B0 - CpuBistData
+ Pointer CPU BIST Data
**/
- UINT8 Reserved28[10];
+ UINT32 CpuBistData;
/** Offset 0x05B4 - CpuMpPpi
<b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
@@ -568,9 +1292,55 @@ typedef struct {
**/
UINT32 CpuMpPpi;
-/** Offset 0x05B8 - Reserved
+/** Offset 0x05B8 - CpuMpHob
+ <b>@deprecated</b> This is not needed in current version of FSP.
**/
- UINT8 Reserved29[46];
+ UINT32 CpuMpHob;
+
+/** Offset 0x05BC - Reserved
+**/
+ UINT8 Reserved32[16];
+
+/** Offset 0x05CC - PpinSupport to view Protected Processor Inventory Number
+ Enable or Disable or Auto (Based on End of Manufacturing flag. Disabled if this
+ flag is set) for PPIN Support
+ 0: Disable, 1: Enable, 2: Auto
+**/
+ UINT8 PpinSupport;
+
+/** Offset 0x05CD - Enable or Disable Minimum Voltage Override
+ Enable or disable Minimum Voltage overrides ; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 EnableMinVoltageOverride;
+
+/** Offset 0x05CE - Min Voltage for Runtime
+ PCODE MMIO Mailbox: Minimum voltage for runtime. Valid if EnableMinVoltageOverride
+ = 1. Range 0 to 1999mV. <b> 0: 0mV </b>
+**/
+ UINT16 MinVoltageRuntime;
+
+/** Offset 0x05D0 - Base of memory region allocated for Processor Trace
+ Base address of memory region allocated for Processor Trace. Processor Trace requires
+ 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
+**/
+ UINT64 ProcessorTraceMemBase;
+
+/** Offset 0x05D8 - Memory region allocation for Processor Trace
+ Length in bytes of memory region allocated for Processor Trace. Processor Trace
+ requires 2^N alignment and size in bytes per thread, from 4KB to 128MB. <b>0: Disable</b>
+**/
+ UINT32 ProcessorTraceMemLength;
+
+/** Offset 0x05DC - Min Voltage for C8
+ PCODE MMIO Mailbox: Minimum voltage for C8. Valid if EnableMinVoltageOverride =
+ 1. Range 0 to 1999mV. <b> 0: 0mV </b>
+**/
+ UINT16 MinVoltageC8;
+
+/** Offset 0x05DE - Reserved
+**/
+ UINT8 Reserved33[8];
/** Offset 0x05E6 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
@@ -578,18 +1348,62 @@ typedef struct {
**/
UINT8 PchPwrOptEnable;
-/** Offset 0x05E7 - Reserved
+/** Offset 0x05E7 - PCH Flash Protection Ranges Write Enble
+ Write or erase is blocked by hardware.
+**/
+ UINT8 PchWriteProtectionEnable[5];
+
+/** Offset 0x05EC - PCH Flash Protection Ranges Read Enble
+ Read is blocked by hardware.
+**/
+ UINT8 PchReadProtectionEnable[5];
+
+/** Offset 0x05F1 - Reserved
+**/
+ UINT8 Reserved34;
+
+/** Offset 0x05F2 - PCH Protect Range Limit
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+ limit comparison.
+**/
+ UINT16 PchProtectedRangeLimit[5];
+
+/** Offset 0x05FC - PCH Protect Range Base
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+ UINT16 PchProtectedRangeBase[5];
+
+/** Offset 0x0606 - Enable Pme
+ Enable Azalia wake-on-ring.
+ $EN_DIS
+**/
+ UINT8 PchHdaPme;
+
+/** Offset 0x0607 - HD Audio Link Frequency
+ HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
+ 0: 6MHz, 1: 12MHz, 2: 24MHz
**/
- UINT8 Reserved30[36];
+ UINT8 PchHdaLinkFrequency;
+
+/** Offset 0x0608 - Reserved
+**/
+ UINT8 Reserved35[3];
/** Offset 0x060B - Enable PCH ISH SPI Cs0 pins assigned
Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
**/
UINT8 PchIshSpiCs0Enable[1];
-/** Offset 0x060C - Reserved
+/** Offset 0x060C - Enable PCH Io Apic Entry 24-119
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIoApicEntry24_119;
+
+/** Offset 0x060D - PCH Io Apic ID
+ This member determines IOAPIC ID. Default is 0x02.
**/
- UINT8 Reserved31[2];
+ UINT8 PchIoApicId;
/** Offset 0x060E - Enable PCH ISH SPI pins assigned
Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
@@ -611,9 +1425,17 @@ typedef struct {
**/
UINT8 PchIshGpEnable[8];
-/** Offset 0x061C - Reserved
+/** Offset 0x061C - PCH ISH PDT Unlock Msg
+ 0: False; 1: True.
+ $EN_DIS
**/
- UINT8 Reserved32[2];
+ UINT8 PchIshPdtUnlock;
+
+/** Offset 0x061D - Enable PCH Lan LTR capabilty of PCH internal LAN
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchLanLtrEnable;
/** Offset 0x061E - Enable LOCKDOWN BIOS LOCK
Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
@@ -622,9 +1444,15 @@ typedef struct {
**/
UINT8 PchLockDownBiosLock;
-/** Offset 0x061F - Reserved
+/** Offset 0x061F - PCH Compatibility Revision ID
+ This member describes whether or not the CRID feature of PCH should be enabled.
+ $EN_DIS
+**/
+ UINT8 PchCrid;
+
+/** Offset 0x0620 - Reserved
**/
- UINT8 Reserved33[2];
+ UINT8 Reserved36;
/** Offset 0x0621 - RTC Cmos Memory Lock
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
@@ -643,9 +1471,10 @@ typedef struct {
**/
UINT8 PcieRpPmSci[24];
-/** Offset 0x0652 - Reserved
+/** Offset 0x0652 - Enable PCIE RP Transmitter Half Swing
+ Indicate whether the Transmitter Half Swing is enabled.
**/
- UINT8 Reserved34[24];
+ UINT8 PcieRpTransmitterHalfSwing[24];
/** Offset 0x066A - Enable PCIE RP Clk Req Detect
Probe CLKREQ# signal before enabling CLKREQ# based power management.
@@ -657,9 +1486,40 @@ typedef struct {
**/
UINT8 PcieRpAdvancedErrorReporting[24];
-/** Offset 0x069A - Reserved
+/** Offset 0x069A - PCIE RP Unsupported Request Report
+ Indicate whether the Unsupported Request Report is enabled.
+**/
+ UINT8 PcieRpUnsupportedRequestReport[24];
+
+/** Offset 0x06B2 - PCIE RP Fatal Error Report
+ Indicate whether the Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpFatalErrorReport[24];
+
+/** Offset 0x06CA - PCIE RP No Fatal Error Report
+ Indicate whether the No Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpNoFatalErrorReport[24];
+
+/** Offset 0x06E2 - PCIE RP Correctable Error Report
+ Indicate whether the Correctable Error Report is enabled.
+**/
+ UINT8 PcieRpCorrectableErrorReport[24];
+
+/** Offset 0x06FA - PCIE RP System Error On Fatal Error
+ Indicate whether the System Error on Fatal Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnFatalError[24];
+
+/** Offset 0x0712 - PCIE RP System Error On Non Fatal Error
+ Indicate whether the System Error on Non Fatal Error is enabled.
**/
- UINT8 Reserved35[168];
+ UINT8 PcieRpSystemErrorOnNonFatalError[24];
+
+/** Offset 0x072A - PCIE RP System Error On Correctable Error
+ Indicate whether the System Error on Correctable Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnCorrectableError[24];
/** Offset 0x0742 - PCIE RP Max Payload
Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX_PAYLOAD.
@@ -674,7 +1534,7 @@ typedef struct {
/** Offset 0x075B - Reserved
**/
- UINT8 Reserved36[5];
+ UINT8 Reserved37[5];
/** Offset 0x0760 - Touch Host Controller Port 1 Assignment
Assign THC Port 1
@@ -684,7 +1544,23 @@ typedef struct {
/** Offset 0x0761 - Reserved
**/
- UINT8 Reserved37[79];
+ UINT8 Reserved38[7];
+
+/** Offset 0x0768 - PCIE RP Pcie Speed
+ Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
+ PCIE_SPEED).
+**/
+ UINT8 PcieRpPcieSpeed[24];
+
+/** Offset 0x0780 - PCIE RP Physical Slot Number
+ Indicates the slot number for the root port. Default is the value as root port index.
+**/
+ UINT8 PcieRpPhysicalSlotNumber[24];
+
+/** Offset 0x0798 - PCIE RP Completion Timeout
+ The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PcieCompletionTO_Default.
+**/
+ UINT8 PcieRpCompletionTimeout[24];
/** Offset 0x07B0 - PCIE RP Aspm
The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
@@ -703,9 +1579,66 @@ typedef struct {
**/
UINT8 PcieRpLtrEnable[24];
-/** Offset 0x07F8 - Reserved
+/** Offset 0x07F8 - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
**/
- UINT8 Reserved38[79];
+ UINT8 PcieRpLtrConfigLock[24];
+
+/** Offset 0x0810 - Reserved
+**/
+ UINT8 Reserved39[45];
+
+/** Offset 0x083D - PCIE Enable Peer Memory Write
+ This member describes whether Peer Memory Writes are enabled on the platform.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePeerMemoryWrite;
+
+/** Offset 0x083E - PCIE Compliance Test Mode
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ $EN_DIS
+**/
+ UINT8 PcieComplianceTestMode;
+
+/** Offset 0x083F - PCIE Rp Function Swap
+ Allows BIOS to use root port function number swapping when root port of function
+ 0 is disabled.
+ $EN_DIS
+**/
+ UINT8 PcieRpFunctionSwap;
+
+/** Offset 0x0840 - Reserved
+**/
+ UINT8 Reserved40[2];
+
+/** Offset 0x0842 - PCH Pm PME_B0_S5_DIS
+ When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
+ $EN_DIS
+**/
+ UINT8 PchPmPmeB0S5Dis;
+
+/** Offset 0x0843 - PCIE IMR
+ Enables Isolated Memory Region for PCIe.
+ $EN_DIS
+**/
+ UINT8 PcieRpImrEnabled;
+
+/** Offset 0x0844 - PCIE IMR port number
+ Selects PCIE root port number for IMR feature.
+**/
+ UINT8 PcieRpImrSelection;
+
+/** Offset 0x0845 - PCH Pm Wol Enable Override
+ Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolEnableOverride;
+
+/** Offset 0x0846 - PCH Pm Pcie Wake From DeepSx
+ Determine if enable PCIe to wake from deep Sx.
+ $EN_DIS
+**/
+ UINT8 PchPmPcieWakeFromDeepSx;
/** Offset 0x0847 - PCH Pm WoW lan Enable
Determine if WLAN wake from Sx, corresponds to the HOST_WLAN_PP_EN bit in the PWRM_CFG3 register.
@@ -726,9 +1659,97 @@ typedef struct {
**/
UINT8 PchPmLanWakeFromDeepSx;
-/** Offset 0x084A - Reserved
+/** Offset 0x084A - PCH Pm Deep Sx Pol
+ Deep Sx Policy.
+ $EN_DIS
+**/
+ UINT8 PchPmDeepSxPol;
+
+/** Offset 0x084B - PCH Pm Slp S3 Min Assert
+ SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
+**/
+ UINT8 PchPmSlpS3MinAssert;
+
+/** Offset 0x084C - PCH Pm Slp S4 Min Assert
+ SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
+**/
+ UINT8 PchPmSlpS4MinAssert;
+
+/** Offset 0x084D - PCH Pm Slp Sus Min Assert
+ SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
+**/
+ UINT8 PchPmSlpSusMinAssert;
+
+/** Offset 0x084E - PCH Pm Slp A Min Assert
+ SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
+**/
+ UINT8 PchPmSlpAMinAssert;
+
+/** Offset 0x084F - USB Overcurrent Override for DbC
+ This option overrides USB Over Current enablement state that USB OC will be disabled
+ after enabling this option. Enable when DbC is used to avoid signaling conflicts.
+ $EN_DIS
+**/
+ UINT8 PchEnableDbcObs;
+
+/** Offset 0x0850 - PCH Pm Slp Strch Sus Up
+ Enable SLP_X Stretching After SUS Well Power Up.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpStrchSusUp;
+
+/** Offset 0x0851 - PCH Pm Slp Lan Low Dc
+ Enable/Disable SLP_LAN# Low on DC Power.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpLanLowDc;
+
+/** Offset 0x0852 - PCH Pm Pwr Btn Override Period
+ PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
+**/
+ UINT8 PchPmPwrBtnOverridePeriod;
+
+/** Offset 0x0853 - PCH Pm Disable Dsx Ac Present Pulldown
+ When Disable, PCH will internal pull down AC_PRESENT in deep SX and during G3 exit.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableDsxAcPresentPulldown;
+
+/** Offset 0x0854 - PCH Pm Disable Native Power Button
+ Power button native mode disable.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableNativePowerButton;
+
+/** Offset 0x0855 - PCH Pm ME_WAKE_STS
+ Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmMeWakeSts;
+
+/** Offset 0x0856 - PCH Pm WOL_OVR_WK_STS
+ Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolOvrWkSts;
+
+/** Offset 0x0857 - PCH Pm Reset Power Cycle Duration
+ Could be customized in the unit of second. Please refer to EDS for all support settings.
+ 0 is default, 1 is 1 second, 2 is 2 seconds, ...
**/
- UINT8 Reserved39[16];
+ UINT8 PchPmPwrCycDur;
+
+/** Offset 0x0858 - PCH Pm Pcie Pll Ssc
+ Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
+ BIOS override.
+**/
+ UINT8 PchPmPciePllSsc;
+
+/** Offset 0x0859 - PCH Legacy IO Low Latency Enable
+ Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchLegacyIoLowLatency;
/** Offset 0x085A - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
@@ -736,9 +1757,41 @@ typedef struct {
**/
UINT8 SataPwrOptEnable;
-/** Offset 0x085B - Reserved
+/** Offset 0x085B - PCH Sata eSATA Speed Limit
+ When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
+ $EN_DIS
+**/
+ UINT8 EsataSpeedLimit;
+
+/** Offset 0x085C - PCH Sata Speed Limit
+ Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
+**/
+ UINT8 SataSpeedLimit;
+
+/** Offset 0x085D - Enable SATA Port HotPlug
+ Enable SATA Port HotPlug.
+**/
+ UINT8 SataPortsHotPlug[8];
+
+/** Offset 0x0865 - Enable SATA Port Interlock Sw
+ Enable SATA Port Interlock Sw.
+**/
+ UINT8 SataPortsInterlockSw[8];
+
+/** Offset 0x086D - Enable SATA Port External
+ Enable SATA Port External.
+**/
+ UINT8 SataPortsExternal[8];
+
+/** Offset 0x0875 - Enable SATA Port SpinUp
+ Enable the COMRESET initialization Sequence to the device.
+**/
+ UINT8 SataPortsSpinUp[8];
+
+/** Offset 0x087D - Enable SATA Port Solid State Drive
+ 0: HDD; 1: SSD.
**/
- UINT8 Reserved40[42];
+ UINT8 SataPortsSolidStateDrive[8];
/** Offset 0x0885 - Enable SATA Port Enable Dito Config
Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
@@ -759,9 +1812,287 @@ typedef struct {
**/
UINT16 SataPortsDitoVal[8];
-/** Offset 0x08A6 - Reserved
+/** Offset 0x08A6 - Enable SATA Port ZpOdd
+ Support zero power ODD.
+**/
+ UINT8 SataPortsZpOdd[8];
+
+/** Offset 0x08AE - PCH Sata Rst Raid Alternate Id
+ Enable RAID Alternate ID.
+ $EN_DIS
+**/
+ UINT8 SataRstRaidDeviceId;
+
+/** Offset 0x08AF - PCH Sata Rst Raid0
+ RAID0.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid0;
+
+/** Offset 0x08B0 - PCH Sata Rst Raid1
+ RAID1.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid1;
+
+/** Offset 0x08B1 - PCH Sata Rst Raid10
+ RAID10.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid10;
+
+/** Offset 0x08B2 - PCH Sata Rst Raid5
+ RAID5.
+ $EN_DIS
+**/
+ UINT8 SataRstRaid5;
+
+/** Offset 0x08B3 - PCH Sata Rst Irrt
+ Intel Rapid Recovery Technology.
+ $EN_DIS
+**/
+ UINT8 SataRstIrrt;
+
+/** Offset 0x08B4 - PCH Sata Rst Orom Ui Banner
+ OROM UI and BANNER.
+ $EN_DIS
+**/
+ UINT8 SataRstOromUiBanner;
+
+/** Offset 0x08B5 - PCH Sata Rst Orom Ui Delay
+ 00b: 2 secs; 01b: 4 secs; 10b: 6 secs; 11: 8 secs (see: PCH_SATA_OROM_DELAY).
+**/
+ UINT8 SataRstOromUiDelay;
+
+/** Offset 0x08B6 - PCH Sata Rst Hdd Unlock
+ Indicates that the HDD password unlock in the OS is enabled.
+ $EN_DIS
+**/
+ UINT8 SataRstHddUnlock;
+
+/** Offset 0x08B7 - PCH Sata Rst Led Locate
+ Indicates that the LED/SGPIO hardware is attached and ping to locate feature is
+ enabled on the OS.
+ $EN_DIS
+**/
+ UINT8 SataRstLedLocate;
+
+/** Offset 0x08B8 - PCH Sata Rst Irrt Only
+ Allow only IRRT drives to span internal and external ports.
+ $EN_DIS
+**/
+ UINT8 SataRstIrrtOnly;
+
+/** Offset 0x08B9 - PCH Sata Rst Smart Storage
+ RST Smart Storage caching Bit.
+ $EN_DIS
**/
- UINT8 Reserved42[72];
+ UINT8 SataRstSmartStorage;
+
+/** Offset 0x08BA - PCH Sata Rst Pcie Storage Remap enable
+ Enable Intel RST for PCIe Storage remapping.
+**/
+ UINT8 SataRstPcieEnable[3];
+
+/** Offset 0x08BD - PCH Sata Rst Pcie Storage Port
+ Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
+**/
+ UINT8 SataRstPcieStoragePort[3];
+
+/** Offset 0x08C0 - PCH Sata Rst Pcie Device Reset Delay
+ PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+**/
+ UINT8 SataRstPcieDeviceResetDelay[3];
+
+/** Offset 0x08C3 - UFS enable/disable
+ PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+ $EN_DIS
+**/
+ UINT8 UfsEnable[2];
+
+/** Offset 0x08C5 - Reserved
+**/
+ UINT8 Reserved42;
+
+/** Offset 0x08C6 - Thermal Throttling Custimized T0Level Value
+ Custimized T0Level value.
+**/
+ UINT16 PchT0Level;
+
+/** Offset 0x08C8 - Thermal Throttling Custimized T1Level Value
+ Custimized T1Level value.
+**/
+ UINT16 PchT1Level;
+
+/** Offset 0x08CA - Thermal Throttling Custimized T2Level Value
+ Custimized T2Level value.
+**/
+ UINT16 PchT2Level;
+
+/** Offset 0x08CC - Enable The Thermal Throttle
+ Enable the thermal throttle function.
+ $EN_DIS
+**/
+ UINT8 PchTTEnable;
+
+/** Offset 0x08CD - PMSync State 13
+ When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
+ at least T2 state.
+ $EN_DIS
+**/
+ UINT8 PchTTState13Enable;
+
+/** Offset 0x08CE - Thermal Throttle Lock
+ Thermal Throttle Lock.
+ $EN_DIS
+**/
+ UINT8 PchTTLock;
+
+/** Offset 0x08CF - Thermal Throttling Suggested Setting
+ Thermal Throttling Suggested Setting.
+ $EN_DIS
+**/
+ UINT8 TTSuggestedSetting;
+
+/** Offset 0x08D0 - Enable PCH Cross Throttling
+ Enable/Disable PCH Cross Throttling
+ $EN_DIS
+**/
+ UINT8 TTCrossThrottling;
+
+/** Offset 0x08D1 - DMI Thermal Sensor Autonomous Width Enable
+ DMI Thermal Sensor Autonomous Width Enable.
+ $EN_DIS
+**/
+ UINT8 PchDmiTsawEn;
+
+/** Offset 0x08D2 - DMI Thermal Sensor Suggested Setting
+ DMT thermal sensor suggested representative values.
+ $EN_DIS
+**/
+ UINT8 DmiSuggestedSetting;
+
+/** Offset 0x08D3 - Thermal Sensor 0 Target Width
+ Thermal Sensor 0 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS0TW;
+
+/** Offset 0x08D4 - Thermal Sensor 1 Target Width
+ Thermal Sensor 1 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS1TW;
+
+/** Offset 0x08D5 - Thermal Sensor 2 Target Width
+ Thermal Sensor 2 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS2TW;
+
+/** Offset 0x08D6 - Thermal Sensor 3 Target Width
+ Thermal Sensor 3 Target Width.
+ 0:x1, 1:x2, 2:x4, 3:x8, 4:x16
+**/
+ UINT8 DmiTS3TW;
+
+/** Offset 0x08D7 - Port 0 T1 Multipler
+ Port 0 T1 Multipler.
+**/
+ UINT8 SataP0T1M;
+
+/** Offset 0x08D8 - Port 0 T2 Multipler
+ Port 0 T2 Multipler.
+**/
+ UINT8 SataP0T2M;
+
+/** Offset 0x08D9 - Port 0 T3 Multipler
+ Port 0 T3 Multipler.
+**/
+ UINT8 SataP0T3M;
+
+/** Offset 0x08DA - Port 0 Tdispatch
+ Port 0 Tdispatch.
+**/
+ UINT8 SataP0TDisp;
+
+/** Offset 0x08DB - Port 1 T1 Multipler
+ Port 1 T1 Multipler.
+**/
+ UINT8 SataP1T1M;
+
+/** Offset 0x08DC - Port 1 T2 Multipler
+ Port 1 T2 Multipler.
+**/
+ UINT8 SataP1T2M;
+
+/** Offset 0x08DD - Port 1 T3 Multipler
+ Port 1 T3 Multipler.
+**/
+ UINT8 SataP1T3M;
+
+/** Offset 0x08DE - Port 1 Tdispatch
+ Port 1 Tdispatch.
+**/
+ UINT8 SataP1TDisp;
+
+/** Offset 0x08DF - Port 0 Tinactive
+ Port 0 Tinactive.
+**/
+ UINT8 SataP0Tinact;
+
+/** Offset 0x08E0 - Port 0 Alternate Fast Init Tdispatch
+ Port 0 Alternate Fast Init Tdispatch.
+ $EN_DIS
+**/
+ UINT8 SataP0TDispFinit;
+
+/** Offset 0x08E1 - Port 1 Tinactive
+ Port 1 Tinactive.
+**/
+ UINT8 SataP1Tinact;
+
+/** Offset 0x08E2 - Port 1 Alternate Fast Init Tdispatch
+ Port 1 Alternate Fast Init Tdispatch.
+ $EN_DIS
+**/
+ UINT8 SataP1TDispFinit;
+
+/** Offset 0x08E3 - Sata Thermal Throttling Suggested Setting
+ Sata Thermal Throttling Suggested Setting.
+ $EN_DIS
+**/
+ UINT8 SataThermalSuggestedSetting;
+
+/** Offset 0x08E4 - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+ $EN_DIS
+**/
+ UINT8 PchMemoryThrottlingEnable;
+
+/** Offset 0x08E5 - Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryPmsyncEnable[2];
+
+/** Offset 0x08E7 - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryC0TransmitEnable[2];
+
+/** Offset 0x08E9 - Enable Memory Thermal Throttling
+ Enable Memory Thermal Throttling.
+**/
+ UINT8 PchMemoryPinSelection[2];
+
+/** Offset 0x08EB - Reserved
+**/
+ UINT8 Reserved43;
+
+/** Offset 0x08EC - Thermal Device Temperature
+ Decides the temperature.
+**/
+ UINT16 PchTemperatureHotLevel;
/** Offset 0x08EE - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
@@ -773,9 +2104,30 @@ typedef struct {
**/
UINT8 Usb3OverCurrentPin[10];
-/** Offset 0x0908 - Reserved
+/** Offset 0x0908 - Enable xHCI LTR override
+ Enables override of recommended LTR values for xHCI
+ $EN_DIS
+**/
+ UINT8 PchUsbLtrOverrideEnable;
+
+/** Offset 0x0909 - Reserved
+**/
+ UINT8 Reserved44[3];
+
+/** Offset 0x090C - xHCI High Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrHighIdleTimeOverride;
+
+/** Offset 0x0910 - xHCI Medium Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrMediumIdleTimeOverride;
+
+/** Offset 0x0914 - xHCI Low Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
**/
- UINT8 Reserved43[16];
+ UINT32 PchUsbLtrLowIdleTimeOverride;
/** Offset 0x0918 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
@@ -793,9 +2145,25 @@ typedef struct {
**/
UINT8 Enable8254ClockGatingOnS3;
-/** Offset 0x091A - Reserved
+/** Offset 0x091A - PCH Sata Rst Optane Memory
+ Optane Memory
+ $EN_DIS
**/
- UINT8 Reserved44[3];
+ UINT8 SataRstOptaneMemory;
+
+/** Offset 0x091B - PCH Sata Rst CPU Attached Storage
+ CPU Attached Storage
+ $EN_DIS
+**/
+ UINT8 SataRstCpuAttachedStorage;
+
+/** Offset 0x091C - Enable TCO timer.
+ When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
+ huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
+ emulation must be enabled, and WDAT table must not be exposed to the OS.
+ $EN_DIS
+**/
+ UINT8 EnableTcoTimer;
/** Offset 0x091D - Hybrid Storage Detection and Configuration Mode
Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration.
@@ -806,16 +2174,140 @@ typedef struct {
/** Offset 0x091E - Reserved
**/
- UINT8 Reserved45[96];
+ UINT8 Reserved45[2];
+
+/** Offset 0x0920 - BgpdtHash[4]
+ BgpdtHash values
+**/
+ UINT64 BgpdtHash[4];
+
+/** Offset 0x0940 - BiosGuardAttr
+ BiosGuardAttr default values
+**/
+ UINT32 BiosGuardAttr;
+
+/** Offset 0x0944 - Reserved
+**/
+ UINT8 Reserved46[4];
+
+/** Offset 0x0948 - BiosGuardModulePtr
+ BiosGuardModulePtr default values
+**/
+ UINT64 BiosGuardModulePtr;
+
+/** Offset 0x0950 - SendEcCmd
+ SendEcCmd function pointer. \n
+ @code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
+ EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
+**/
+ UINT64 SendEcCmd;
+
+/** Offset 0x0958 - EcCmdProvisionEav
+ Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
+**/
+ UINT8 EcCmdProvisionEav;
+
+/** Offset 0x0959 - EcCmdLock
+ EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
+**/
+ UINT8 EcCmdLock;
+
+/** Offset 0x095A - Reserved
+**/
+ UINT8 Reserved47[6];
+
+/** Offset 0x0960 - SgxEpoch0
+ SgxEpoch0 default values
+**/
+ UINT64 SgxEpoch0;
+
+/** Offset 0x0968 - SgxEpoch1
+ SgxEpoch1 default values
+**/
+ UINT64 SgxEpoch1;
+
+/** Offset 0x0970 - SgxSinitNvsData
+ SgxSinitNvsData default values
+**/
+ UINT8 SgxSinitNvsData;
+
+/** Offset 0x0971 - Si Config CSM Flag.
+ Platform specific common policies that used by several silicon components. CSM status flag.
+ $EN_DIS
+**/
+ UINT8 SiCsmFlag;
+
+/** Offset 0x0972 - Reserved
+**/
+ UINT8 Reserved48[6];
+
+/** Offset 0x0978 - SVID SDID table Poniter.
+ The address of the table of SVID SDID to customize each SVID SDID entry. This is
+ only valid when SkipSsidProgramming is FALSE.
+**/
+ UINT32 SiSsidTablePtr;
+
+/** Offset 0x097C - Number of ssid table.
+ SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
+ This is only valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiNumberOfSsidTableEntry;
/** Offset 0x097E - USB2 Port Reset Message Enable
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message
**/
UINT8 PortResetMessageEnable[16];
-/** Offset 0x098E - Reserved
+/** Offset 0x098E - SATA RST Interrupt Mode
+ Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
+ 0:Msix, 1:Msi, 2:Legacy
+**/
+ UINT8 SataRstInterrupt;
+
+/** Offset 0x098F - ME Unconfig on RTC clear
+ 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
+ 2: Cmos is clear, status unkonwn. 3: Reserved
+ 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
+ is clear, 3: Reserved
+**/
+ UINT8 MeUnconfigOnRtcClear;
+
+/** Offset 0x0990 - Enable PS_ON.
+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
+ target that will be required by the California Energy Commission (CEC). When FALSE,
+ PS_ON is to be disabled.
+ $EN_DIS
**/
- UINT8 Reserved46[322];
+ UINT8 PsOnEnable;
+
+/** Offset 0x0991 - Pmc Cpu C10 Gate Pin Enable
+ Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
+ and VccSTG rails instead of SLP_S0# pin.
+ $EN_DIS
+**/
+ UINT8 PmcCpuC10GatePinEnable;
+
+/** Offset 0x0992 - Pch Dmi Aspm Ctrl
+ ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
+ 0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
+**/
+ UINT8 PchDmiAspmCtrl;
+
+/** Offset 0x0993 - PchDmiCwbEnable
+ Central Write Buffer feature configurable and enabled by default
+ $EN_DIS
+**/
+ UINT8 PchDmiCwbEnable;
+
+/** Offset 0x0994 - OS IDLE Mode Enable
+ Enable/Disable OS Idle Mode
+ $EN_DIS
+**/
+ UINT8 PmcOsIdleEnable;
+
+/** Offset 0x0995 - Reserved
+**/
+ UINT8 Reserved49[315];
/** Offset 0x0AD0 - RpPtmBytes
**/
@@ -823,7 +2315,19 @@ typedef struct {
/** Offset 0x0AD4 - Reserved
**/
- UINT8 Reserved47[36];
+ UINT8 Reserved50[16];
+
+/** Offset 0x0AE4 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate3UniqTranEnable[10];
+
+/** Offset 0x0AEE - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
+ = 4Ch</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate3UniqTran[10];
/** Offset 0x0AF8 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
@@ -837,9 +2341,61 @@ typedef struct {
**/
UINT8 Usb3HsioTxRate2UniqTran[10];
-/** Offset 0x0B0C - Reserved
+/** Offset 0x0B0C - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate1UniqTranEnable[10];
+
+/** Offset 0x0B16 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
+ <b>Default = 4Ch</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate1UniqTran[10];
+
+/** Offset 0x0B20 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate0UniqTranEnable[10];
+
+/** Offset 0x0B2A - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
+ <b>Default = 4Ch</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate0UniqTran[10];
+
+/** Offset 0x0B34 - Skip PAM regsiter lock
+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+ PAM registers will be locked by RC
+ $EN_DIS
+**/
+ UINT8 SkipPamLock;
+
+/** Offset 0x0B35 - EDRAM Test Mode
+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+ PAM registers will be locked by RC
+ 0: EDRAM SW disable, 1: EDRAM SW Enable, 2: EDRAM HW mode
+**/
+ UINT8 EdramTestMode;
+
+/** Offset 0x0B36 - Enable/Disable IGFX RenderStandby
+ Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
+ $EN_DIS
+**/
+ UINT8 RenderStandby;
+
+/** Offset 0x0B37 - Enable/Disable IGFX PmSupport
+ Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
+ $EN_DIS
**/
- UINT8 Reserved48[45];
+ UINT8 PmSupport;
+
+/** Offset 0x0B38 - Enable/Disable CdynmaxClamp
+ Enable: Enable CdynmaxClamp, Disable(Default): Disable CdynmaxClamp
+ $EN_DIS
+**/
+ UINT8 CdynmaxClampEnable;
/** Offset 0x0B39 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
@@ -855,9 +2411,103 @@ typedef struct {
**/
UINT8 GtFreqMax;
-/** Offset 0x0B3A - Reserved
+/** Offset 0x0B3A - Disable Turbo GT
+ 0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
+ $EN_DIS
**/
- UINT8 Reserved49[31];
+ UINT8 DisableTurboGt;
+
+/** Offset 0x0B3B - Enable/Disable CdClock Init
+ Enable: Skip Full CD clock initializaton, Disable(Default): Initialize the full
+ CD clock if not initialized by Gfx PEIM
+ $EN_DIS
+**/
+ UINT8 SkipCdClockInit;
+
+/** Offset 0x0B3C - Reserved
+**/
+ UINT8 Reserved51[16];
+
+/** Offset 0x0B4C - 1-Core Ratio Limit
+ 1-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 1-Core Ratio Limit + OC Bins.This 1-Core Ratio Limit Must be greater than or equal
+ to 2-Core Ratio Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. Range is 0 to 83
+**/
+ UINT8 OneCoreRatioLimit;
+
+/** Offset 0x0B4D - 2-Core Ratio Limit
+ 2-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 2-Core Ratio Limit + OC Bins.This 2-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 TwoCoreRatioLimit;
+
+/** Offset 0x0B4E - 3-Core Ratio Limit
+ 3-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 3-Core Ratio Limit + OC Bins.This 3-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 ThreeCoreRatioLimit;
+
+/** Offset 0x0B4F - 4-Core Ratio Limit
+ 4-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 4-Core Ratio Limit + OC Bins.This 4-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+**/
+ UINT8 FourCoreRatioLimit;
+
+/** Offset 0x0B50 - Enable or Disable HWP
+ Enable or Disable HWP(Hardware P states) Support. 0: Disable; <b>1: Enable;</b>
+ 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 Hwp;
+
+/** Offset 0x0B51 - Hardware Duty Cycle Control
+ Hardware Duty Cycle Control configuration. 0: Disabled; <b>1: Enabled</b> 2-3:Reserved
+ $EN_DIS
+**/
+ UINT8 HdcControl;
+
+/** Offset 0x0B52 - Package Long duration turbo mode time
+ Package Long duration turbo mode time window in seconds. Valid values(Unit in seconds)
+ 0 to 8 , 10 , 12 ,14 , 16 , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+ UINT8 PowerLimit1Time;
+
+/** Offset 0x0B53 - Short Duration Turbo Mode
+ Enable or Disable short duration Turbo Mode. </b>0 : Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 PowerLimit2;
+
+/** Offset 0x0B54 - Turbo settings Lock
+ Lock all Turbo settings Enable/Disable; <b>0: Disable , </b> 1: Enable
+ $EN_DIS
+**/
+ UINT8 TurboPowerLimitLock;
+
+/** Offset 0x0B55 - Package PL3 time window
+ Package PL3 time window range for this policy from 0 to 64ms
+**/
+ UINT8 PowerLimit3Time;
+
+/** Offset 0x0B56 - Package PL3 Duty Cycle
+ Package PL3 Duty Cycle; Valid Range is 0 to 100
+**/
+ UINT8 PowerLimit3DutyCycle;
+
+/** Offset 0x0B57 - Package PL3 Lock
+ Package PL3 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit3Lock;
+
+/** Offset 0x0B58 - Package PL4 Lock
+ Package PL4 Lock Enable/Disable; <b>0: Disable</b> ; 1:Enable
+ $EN_DIS
+**/
+ UINT8 PowerLimit4Lock;
/** Offset 0x0B59 - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
@@ -882,9 +2532,273 @@ typedef struct {
**/
UINT8 TccOffsetLock;
-/** Offset 0x0B5C - Reserved
+/** Offset 0x0B5C - Custom Ratio State Entries
+ The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
+ ratio table.Sets the number of custom P-states. At least 2 states must be present
+**/
+ UINT8 NumberOfEntries;
+
+/** Offset 0x0B5D - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 1. Valid Range 0 to 128
+**/
+ UINT8 Custom1PowerLimit1Time;
+
+/** Offset 0x0B5E - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 1. Valid Range 0 to 255
+**/
+ UINT8 Custom1TurboActivationRatio;
+
+/** Offset 0x0B5F - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom1ConfigTdpControl;
+
+/** Offset 0x0B60 - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 2. Valid Range 0 to 128
+**/
+ UINT8 Custom2PowerLimit1Time;
+
+/** Offset 0x0B61 - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 2. Valid Range 0 to 255
+**/
+ UINT8 Custom2TurboActivationRatio;
+
+/** Offset 0x0B62 - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom2ConfigTdpControl;
+
+/** Offset 0x0B63 - Custom Short term Power Limit time window
+ Short term Power Limit time window value for custom CTDP level 3. Valid Range 0 to 128
+**/
+ UINT8 Custom3PowerLimit1Time;
+
+/** Offset 0x0B64 - Custom Turbo Activation Ratio
+ Turbo Activation Ratio for custom cTDP level 3. Valid Range 0 to 255
+**/
+ UINT8 Custom3TurboActivationRatio;
+
+/** Offset 0x0B65 - Custom Config Tdp Control
+ Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
+**/
+ UINT8 Custom3ConfigTdpControl;
+
+/** Offset 0x0B66 - ConfigTdp mode settings Lock
+ Lock the ConfigTdp mode settings from runtime changes; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ConfigTdpLock;
+
+/** Offset 0x0B67 - Load Configurable TDP SSDT
+ Configure whether to load Configurable TDP SSDT; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ConfigTdpBios;
+
+/** Offset 0x0B68 - PL1 Enable value
+ PL1 Enable value to limit average platform power. <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PsysPowerLimit1;
+
+/** Offset 0x0B69 - PL1 timewindow
+ PL1 timewindow in seconds.Valid values(Unit in seconds) 0 to 8 , 10 , 12 ,14 , 16
+ , 20 , 24 , 28 , 32 , 40 , 48 , 56 , 64 , 80 , 96 , 112 , 128
+**/
+ UINT8 PsysPowerLimit1Time;
+
+/** Offset 0x0B6A - PL2 Enable Value
+ PL2 Enable activates the PL2 value to limit average platform power.<b>0: Disable</b>;
+ 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PsysPowerLimit2;
+
+/** Offset 0x0B6B - Enable or Disable MLC Streamer Prefetcher
+ Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 MlcStreamerPrefetcher;
+
+/** Offset 0x0B6C - Enable or Disable MLC Spatial Prefetcher
+ Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 MlcSpatialPrefetcher;
+
+/** Offset 0x0B6D - Enable or Disable Monitor /MWAIT instructions
+ Enable or Disable Monitor /MWAIT instructions; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
**/
- UINT8 Reserved50[46];
+ UINT8 MonitorMwaitEnable;
+
+/** Offset 0x0B6E - Enable or Disable initialization of machine check registers
+ Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 MachineCheckEnable;
+
+/** Offset 0x0B6F - AP Idle Manner of waiting for SIPI
+ AP Idle Manner of waiting for SIPI; 1: HALT loop; <b>2: MWAIT loop</b>; 3: RUN loop.
+ 1: HALT loop, 2: MWAIT loop, 3: RUN loop
+**/
+ UINT8 ApIdleManner;
+
+/** Offset 0x0B70 - Control on Processor Trace output scheme
+ Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
+ 0: Single Range Output, 1: ToPA Output
+**/
+ UINT8 ProcessorTraceOutputScheme;
+
+/** Offset 0x0B71 - Enable or Disable Processor Trace feature
+ Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ProcessorTraceEnable;
+
+/** Offset 0x0B72 - Enable or Disable Intel SpeedStep Technology
+ Enable or Disable Intel SpeedStep Technology. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 Eist;
+
+/** Offset 0x0B73 - Enable or Disable Energy Efficient P-state
+ Enable or Disable Energy Efficient P-state will be applied in Turbo mode. Disable;
+ <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientPState;
+
+/** Offset 0x0B74 - Enable or Disable Energy Efficient Turbo
+ Enable or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable;
+ <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientTurbo;
+
+/** Offset 0x0B75 - Enable or Disable T states
+ Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TStates;
+
+/** Offset 0x0B76 - Enable or Disable Bi-Directional PROCHOT#
+ Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 BiProcHot;
+
+/** Offset 0x0B77 - Enable or Disable PROCHOT# signal being driven externally
+ Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 DisableProcHotOut;
+
+/** Offset 0x0B78 - Enable or Disable PROCHOT# Response
+ Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ProcHotResponse;
+
+/** Offset 0x0B79 - Enable or Disable VR Thermal Alert
+ Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 DisableVrThermalAlert;
+
+/** Offset 0x0B7A - Reserved
+**/
+ UINT8 Reserved52;
+
+/** Offset 0x0B7B - Enable or Disable Thermal Monitor
+ Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 ThermalMonitor;
+
+/** Offset 0x0B7C - Enable or Disable CPU power states (C-states)
+ Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 Cx;
+
+/** Offset 0x0B7D - Configure C-State Configuration Lock
+ Configure C-State Configuration Lock; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 PmgCstCfgCtrlLock;
+
+/** Offset 0x0B7E - Enable or Disable Enhanced C-states
+ Enable or Disable Enhanced C-states. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C1e;
+
+/** Offset 0x0B7F - Enable or Disable Package Cstate Demotion
+ Enable or Disable Package Cstate Demotion. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 PkgCStateDemotion;
+
+/** Offset 0x0B80 - Enable or Disable Package Cstate UnDemotion
+ Enable or Disable Package Cstate UnDemotion. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 PkgCStateUnDemotion;
+
+/** Offset 0x0B81 - Enable or Disable CState-Pre wake
+ Enable or Disable CState-Pre wake. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 CStatePreWake;
+
+/** Offset 0x0B82 - Enable or Disable TimedMwait Support.
+ Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 TimedMwait;
+
+/** Offset 0x0B83 - Enable or Disable IO to MWAIT redirection
+ Enable or Disable IO to MWAIT redirection; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 CstCfgCtrIoMwaitRedirection;
+
+/** Offset 0x0B84 - Set the Max Pkg Cstate
+ Set the Max Pkg Cstate. Default set to Auto which limits the Max Pkg Cstate to deep
+ C-state. Valid values 0 - C0/C1 , 1 - C2 , 2 - C3 , 3 - C6 , 4 - C7 , 5 - C7S ,
+ 6 - C8 , 7 - C9 , 8 - C10 , 254 - CPU Default , 255 - Auto
+**/
+ UINT8 PkgCStateLimit;
+
+/** Offset 0x0B85 - TimeUnit for C-State Latency Control0
+ TimeUnit for C-State Latency Control0; Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl0TimeUnit;
+
+/** Offset 0x0B86 - TimeUnit for C-State Latency Control1
+ TimeUnit for C-State Latency Control1;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl1TimeUnit;
+
+/** Offset 0x0B87 - TimeUnit for C-State Latency Control2
+ TimeUnit for C-State Latency Control2;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl2TimeUnit;
+
+/** Offset 0x0B88 - TimeUnit for C-State Latency Control3
+ TimeUnit for C-State Latency Control3;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
+ , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl3TimeUnit;
+
+/** Offset 0x0B89 - TimeUnit for C-State Latency Control4
+ Time - 1ns , 1 - 32ns , 2 - 1024ns , 3 - 32768ns , 4 - 1048576ns , 5 - 33554432ns
+**/
+ UINT8 CstateLatencyControl4TimeUnit;
/** Offset 0x0B8A - TimeUnit for C-State Latency Control5
TimeUnit for C-State Latency Control5;Valid values 0 - 1ns , 1 - 32ns , 2 - 1024ns
@@ -892,9 +2806,107 @@ typedef struct {
**/
UINT8 CstateLatencyControl5TimeUnit;
-/** Offset 0x0B8B - Reserved
+/** Offset 0x0B8B - Interrupt Redirection Mode Select
+ Interrupt Redirection Mode Select.0: Fixed priority; 1: Round robin;2: Hash vector;7:
+ No change.
+**/
+ UINT8 PpmIrmSetting;
+
+/** Offset 0x0B8C - Lock prochot configuration
+ Lock prochot configuration Enable/Disable; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 ProcHotLock;
+
+/** Offset 0x0B8D - Configuration for boot TDP selection
+ Deprecated. Move to premem.
+**/
+ UINT8 ConfigTdpLevel;
+
+/** Offset 0x0B8E - Max P-State Ratio
+ Max P-State Ratio, Valid Range 0 to 0x7F
+**/
+ UINT8 MaxRatio;
+
+/** Offset 0x0B8F - P-state ratios for custom P-state table
+ P-state ratios for custom P-state table. NumberOfEntries has valid range between
+ 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
+ are configurable. Valid Range of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatio[40];
+
+/** Offset 0x0BB7 - P-state ratios for max 16 version of custom P-state table
+ P-state ratios for max 16 version of custom P-state table. This table is used for
+ OS versions limited to a max of 16 P-States. If the first entry of this table is
+ 0, or if Number of Entries is 16 or less, then this table will be ignored, and
+ up to the top 16 values of the StateRatio table will be used instead. Valid Range
+ of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatioMax16[16];
+
+/** Offset 0x0BC7 - Reserved
+**/
+ UINT8 Reserved53;
+
+/** Offset 0x0BC8 - Platform Power Pmax
+ PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
+ Range 0-1024 Watts. Value of 800 = 100W
+**/
+ UINT16 PsysPmax;
+
+/** Offset 0x0BCA - Interrupt Response Time Limit of C-State LatencyContol1
+ Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl1Irtl;
+
+/** Offset 0x0BCC - Interrupt Response Time Limit of C-State LatencyContol2
+ Interrupt Response Time Limit of C-State LatencyContol2.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl2Irtl;
+
+/** Offset 0x0BCE - Interrupt Response Time Limit of C-State LatencyContol3
+ Interrupt Response Time Limit of C-State LatencyContol3.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl3Irtl;
+
+/** Offset 0x0BD0 - Interrupt Response Time Limit of C-State LatencyContol4
+ Interrupt Response Time Limit of C-State LatencyContol4.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl4Irtl;
+
+/** Offset 0x0BD2 - Interrupt Response Time Limit of C-State LatencyContol5
+ Interrupt Response Time Limit of C-State LatencyContol5.Range of value 0 to 0x3FF.
+ 0 is Auto.
+**/
+ UINT16 CstateLatencyControl5Irtl;
+
+/** Offset 0x0BD4 - Package Long duration turbo mode power limit
+ Package Long duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
+ Valid Range 0 to 4095875 in Step size of 125
**/
- UINT8 Reserved51[89];
+ UINT32 PowerLimit1;
+
+/** Offset 0x0BD8 - Package Short duration turbo mode power limit
+ Package Short duration turbo mode power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit2Power;
+
+/** Offset 0x0BDC - Package PL3 power limit
+ Package PL3 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit3;
+
+/** Offset 0x0BE0 - Package PL4 power limit
+ Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 PowerLimit4;
/** Offset 0x0BE4 - Tcc Offset Time Window for RATL
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
@@ -902,9 +2914,200 @@ typedef struct {
**/
UINT32 TccOffsetTimeWindowForRatl;
-/** Offset 0x0BE8 - Reserved
+/** Offset 0x0BE8 - Short term Power Limit value for custom cTDP level 1
+ Short term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom1PowerLimit1;
+
+/** Offset 0x0BEC - Long term Power Limit value for custom cTDP level 1
+ Long term Power Limit value for custom cTDP level 1. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
**/
- UINT8 Reserved52[86];
+ UINT32 Custom1PowerLimit2;
+
+/** Offset 0x0BF0 - Short term Power Limit value for custom cTDP level 2
+ Short term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom2PowerLimit1;
+
+/** Offset 0x0BF4 - Long term Power Limit value for custom cTDP level 2
+ Long term Power Limit value for custom cTDP level 2. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom2PowerLimit2;
+
+/** Offset 0x0BF8 - Short term Power Limit value for custom cTDP level 3
+ Short term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom3PowerLimit1;
+
+/** Offset 0x0BFC - Long term Power Limit value for custom cTDP level 3
+ Long term Power Limit value for custom cTDP level 3. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
+ Range 0 to 4095875 in Step size of 125
+**/
+ UINT32 Custom3PowerLimit2;
+
+/** Offset 0x0C00 - Platform PL1 power
+ Platform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+ 0 to 4095875 in Step size of 125
+**/
+ UINT32 PsysPowerLimit1Power;
+
+/** Offset 0x0C04 - Platform PL2 power
+ Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid Range
+ 0 to 4095875 in Step size of 125
+**/
+ UINT32 PsysPowerLimit2Power;
+
+/** Offset 0x0C08 - Race To Halt
+ Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
+ in order to enter pkg C-State faster to reduce overall power. (RTH is controlled
+ through MSR 1FC bit 20)Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 RaceToHalt;
+
+/** Offset 0x0C09 - Set Three Strike Counter Disable
+ False (default): Three Strike counter will be incremented and True: Prevents Three
+ Strike counter from incrementing; <b>0: False</b>; 1: True.
+ 0: False, 1: True
+**/
+ UINT8 ThreeStrikeCounterDisable;
+
+/** Offset 0x0C0A - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+ Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 HwpInterruptControl;
+
+/** Offset 0x0C0B - 5-Core Ratio Limit
+ 5-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 5-Core Ratio Limit + OC Bins.This 5-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 FiveCoreRatioLimit;
+
+/** Offset 0x0C0C - 6-Core Ratio Limit
+ 6-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 6-Core Ratio Limit + OC Bins.This 6-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 SixCoreRatioLimit;
+
+/** Offset 0x0C0D - 7-Core Ratio Limit
+ 7-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 7-Core Ratio Limit + OC Bins.This 7-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 SevenCoreRatioLimit;
+
+/** Offset 0x0C0E - 8-Core Ratio Limit
+ 8-Core Ratio Limit: For XE part: LFM to 255, For overclocking part: LFM to Fused
+ 8-Core Ratio Limit + OC Bins.This 8-Core Ratio Limit Must be Less than or equal
+ to 1-Core Ratio Limit.Range is 0 to 83
+ 0x0:0xFF
+**/
+ UINT8 EightCoreRatioLimit;
+
+/** Offset 0x0C0F - Intel Turbo Boost Max Technology 3.0
+ Intel Turbo Boost Max Technology 3.0. 0: Disabled; <b>1: Enabled</b>
+ $EN_DIS
+**/
+ UINT8 EnableItbm;
+
+/** Offset 0x0C10 - Intel Turbo Boost Max Technology 3.0 Driver
+ @Deprecated: Intel Turbo Boost Max Technology 3.0 Driver doesn't support for TGL
+ $EN_DIS
+**/
+ UINT8 EnableItbmDriver;
+
+/** Offset 0x0C11 - Enable or Disable C1 Cstate Demotion
+ Enable or Disable C1 Cstate Demotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C1StateAutoDemotion;
+
+/** Offset 0x0C12 - Enable or Disable C1 Cstate UnDemotion
+ Enable or Disable C1 Cstate UnDemotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C1StateUnDemotion;
+
+/** Offset 0x0C13 - Minimum Ring ratio limit override
+ Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MinRingRatioLimit;
+
+/** Offset 0x0C14 - Maximum Ring ratio limit override
+ Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MaxRingRatioLimit;
+
+/** Offset 0x0C15 - Enable or Disable Per Core P State OS control
+ Enable or Disable Per Core P State OS control. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnablePerCorePState;
+
+/** Offset 0x0C16 - Enable or Disable HwP Autonomous Per Core P State OS control
+ Enable or Disable HwP Autonomous Per Core P State OS control. 0: Disable; <b>1:
+ Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnableHwpAutoPerCorePstate;
+
+/** Offset 0x0C17 - Enable or Disable HwP Autonomous EPP Grouping
+ Enable or Disable HwP Autonomous EPP Grouping. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnableHwpAutoEppGrouping;
+
+/** Offset 0x0C18 - Enable or Disable EPB override over PECI
+ Enable or Disable EPB override over PECI. <b>0: Disable;</b> 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnableEpbPeciOverride;
+
+/** Offset 0x0C19 - Enable or Disable Fast MSR for IA32_HWP_REQUEST
+ Enable or Disable Fast MSR for IA32_HWP_REQUEST. 0: Disable;<b> 1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnableFastMsrHwpReq;
+
+/** Offset 0x0C1A - Reserved
+**/
+ UINT8 Reserved54[17];
+
+/** Offset 0x0C2B - SgxSinitDataFromTpm
+ SgxSinitDataFromTpm default values
+**/
+ UINT8 SgxSinitDataFromTpm;
+
+/** Offset 0x0C2C - Reserved
+**/
+ UINT8 Reserved55[16];
+
+/** Offset 0x0C3C - End of Post message
+ Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
+ EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
+ 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
+**/
+ UINT8 EndOfPostMessage;
+
+/** Offset 0x0C3D - D0I3 Setting for HECI Disable
+ Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
+ HECI devices
+ $EN_DIS
+**/
+ UINT8 DisableD0I3SettingForHeci;
/** Offset 0x0C3E - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
@@ -924,9 +3127,12 @@ typedef struct {
**/
UINT8 PchUnlockGpioPads;
-/** Offset 0x0C41 - Reserved
+/** Offset 0x0C41 - PCH Unlock SideBand access
+ The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
+ 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
+ $EN_DIS
**/
- UINT8 Reserved53;
+ UINT8 PchSbAccessUnlock;
/** Offset 0x0C42 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
@@ -938,17 +3144,90 @@ typedef struct {
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[24];
-/** Offset 0x0CA2 - Reserved
+/** Offset 0x0CA2 - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMode[24];
+
+/** Offset 0x0CBA - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x0CD2 - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 PcieRpSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0D02 - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMode[24];
+
+/** Offset 0x0D1A - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[24];
+
+/** Offset 0x0D32 - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0D62 - PCIE RP Slot Power Limit Scale
+ Specifies scale used for slot power limit value. Leave as 0 to set to default.
+**/
+ UINT8 PcieRpSlotPowerLimitScale[24];
+
+/** Offset 0x0D7A - PCIE RP Slot Power Limit Value
+ Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
+**/
+ UINT16 PcieRpSlotPowerLimitValue[24];
+
+/** Offset 0x0DAA - PCIE RP Enable Port8xh Decode
+ This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
+ 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePort8xhDecode;
+
+/** Offset 0x0DAB - PCIE Port8xh Decode Port Index
+ The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
+**/
+ UINT8 PchPciePort8xhDecodePortIndex;
+
+/** Offset 0x0DAC - PCH Energy Reporting
+ Disable/Enable PCH to CPU energy report feature.
+ $EN_DIS
**/
- UINT8 Reserved54[269];
+ UINT8 PchPmDisableEnergyReport;
+
+/** Offset 0x0DAD - PCH Sata Test Mode
+ Allow entrance to the PCH SATA test modes.
+ $EN_DIS
+**/
+ UINT8 SataTestMode;
+
+/** Offset 0x0DAE - PCH USB OverCurrent mapping lock enable
+ If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
+ that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
+ $EN_DIS
+**/
+ UINT8 PchXhciOcLock;
/** Offset 0x0DAF - LpmStateEnableMask
**/
UINT8 LpmStateEnableMask;
-/** Offset 0x0DB0 - Reserved
+/** Offset 0x0DB0 - Mctp Broadcast Cycle
+ Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MctpBroadcastCycle;
+
+/** Offset 0x0DB1 - Reserved
**/
- UINT8 Reserved55[232];
+ UINT8 Reserved56[231];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@@ -965,7 +3244,7 @@ typedef struct {
/** Offset 0x0E98
**/
- UINT8 UnusedUpdSpace36[6];
+ UINT8 UnusedUpdSpace35[6];
/** Offset 0x0E9E
**/
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 06:59:36 +0000