diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-02-13 17:33:18 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@tutanota.com> | 2022-05-16 02:53:59 +0000 |
| commit | 90e4d744ccdd280007c3f83376a18818da681ab9 (patch) | |
| tree | 9e5ff4d939d9a04b4c9a42ff2b629f86b8085a16 /src/vendorcode | |
| parent | ae2c045733daa9100b1fdcbcc58dbd81529c6665 (diff) | |
amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h: Correct SPD_PERSONALITY_BYTE
Regarding Annex K: Serial Presence Detect (SPD) for DDR3 SDRAM Modules
DDR3 - Document Release 6 (JEDEC Standard No. 21-C Page 4.1.2.11 – 69)
memory buffer personality bytes is located at bytes 102 ~ 116.
Change-Id: I7d225fb5e80b537b4c0ce1c23b7a4524e9109a7b
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Diffstat (limited to 'src/vendorcode')
| -rw-r--r-- | src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h index 654a467db2..6826588e89 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtlrdimm3.h @@ -103,7 +103,7 @@ #define SPD_MDQ_800_1066 72 #define SPD_QXODT_800_1066 73 #define SPD_MR1_MR2_800_1066 77 -#define SPD_PERSONALITY_BYTE 150 +#define SPD_PERSONALITY_BYTE 102 #define SPD_FREQ_DIFF_OFFSET 6 |