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authorRonak Kanabar <ronak.kanabar@intel.com>2024-09-24 11:35:49 +0530
committerSubrata Banik <subratabanik@google.com>2024-09-28 18:09:34 +0000
commit7e5765710aca8a322eb76707733b530ad0918353 (patch)
tree8e561f62c7135533a6d295148bec99f43039346b /src/vendorcode
parent76a16f8e8a3a0b8cb32a6ef3063ac071d41c487c (diff)
vc/intel/fsp: Update PTL FSP headers from dummy headers to v2382_01
Update generated FSP headers for Panther Lake from v2382_01 Changes include: - Update FspmUpd.h, FspsUpd.h, MemInfoHob.h and FirmwareVersionInfo.h BUG=b:348678529 TEST=Able to build google/fatcat Change-Id: Ibe382615db1a7c7a0841d8fe4ae43c226e2c2020 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h14
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h2863
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h2245
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h255
4 files changed, 5356 insertions, 21 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h
index ec19ec141b..085b246b92 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FirmwareVersionInfo.h
@@ -1,16 +1,8 @@
/** @file
- Header file for Firmware Version Information
+ Intel Firmware Version Info (FVI) related definitions.
- @copyright
- Copyright (c) 2015 - 2024, Intel Corporation. All rights reserved.<BR>
-
- This program and the accompanying materials are licensed and made available under
- the terms and conditions of the BSD License which accompanies this distribution.
- The full text of the license may be found at
- http://opensource.org/licenses/bsd-license.php
-
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+ Copyright (c) 2024, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
index 4c98fa88ad..226910dff1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspmUpd.h
@@ -40,10 +40,2863 @@ are permitted provided that the following conditions are met:
#include <MemInfoHob.h>
-/** FSP M Configuration
+///
+/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
+///
+typedef struct {
+ UINT8 Revision; ///< Chipset Init Info Revision
+ UINT8 Rsvd[3]; ///< Reserved
+ UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
+ UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
+} CHIPSET_INIT_INFO;
+
+
+/** Fsp M Configuration
**/
typedef struct {
- /* Placeholder for FSP_M_CONFIG UPDs */
+
+/** Offset 0x0060 - Serial Io Uart Debug Mode
+ Select SerialIo Uart Controller mode
+ 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartDebugMode;
+
+/** Offset 0x0061 - Serial Io Uart Debug Auto Flow
+ Enables UART hardware flow control, CTS and RTS lines.
+ $EN_DIS
+**/
+ UINT8 SerialIoUartDebugAutoFlow;
+
+/** Offset 0x0062 - Reserved
+**/
+ UINT8 Reserved0[2];
+
+/** Offset 0x0064 - SerialIoUartDebugRxPinMux - FSPT
+ Select RX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 SerialIoUartDebugRxPinMux;
+
+/** Offset 0x0068 - SerialIoUartDebugTxPinMux - FSPM
+ Select TX pin muxing for SerialIo UART used for debug
+**/
+ UINT32 SerialIoUartDebugTxPinMux;
+
+/** Offset 0x006C - SerialIoUartDebugRtsPinMux - FSPM
+ Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartDebugRtsPinMux;
+
+/** Offset 0x0070 - SerialIoUartDebugCtsPinMux - FSPM
+ Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartDebugCtsPinMux;
+
+/** Offset 0x0074 - Reserved
+**/
+ UINT8 Reserved1;
+
+/** Offset 0x0075 - DCI Enable
+ Determine if to enable DCI debug from host
+ $EN_DIS
+**/
+ UINT8 DciEn;
+
+/** Offset 0x0076 - DCI DbC Mode
+ Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both:
+ Set both USB2/3DBCEN; No Change: Comply with HW value
+ 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change
+**/
+ UINT8 DciDbcMode;
+
+/** Offset 0x0077 - Reserved
+**/
+ UINT8 Reserved2[3];
+
+/** Offset 0x007A - Memory Test on Warm Boot
+ Run Base Memory Test on Warm Boot
+ 0:Disable, 1:Enable
+**/
+ UINT8 MemTestOnWarmBoot;
+
+/** Offset 0x007B - Reserved
+**/
+ UINT8 Reserved3[5];
+
+/** Offset 0x0080 - Platform Reserved Memory Size
+ The minimum platform memory size required to pass control into DXE
+**/
+ UINT64 PlatformMemorySize;
+
+/** Offset 0x0088 - SPD Data Length
+ Length of SPD Data
+ 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes
+**/
+ UINT16 MemorySpdDataLen;
+
+/** Offset 0x008A - Reserved
+**/
+ UINT8 Reserved4[6];
+
+/** Offset 0x0090 - Memory SPD Pointer Controller 0 Channel 0 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr000;
+
+/** Offset 0x0098 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr001;
+
+/** Offset 0x00A0 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr010;
+
+/** Offset 0x00A8 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr011;
+
+/** Offset 0x00B0 - Memory SPD Pointer Controller 0 Channel 2 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr020;
+
+/** Offset 0x00B8 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr021;
+
+/** Offset 0x00C0 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr030;
+
+/** Offset 0x00C8 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr031;
+
+/** Offset 0x00D0 - Memory SPD Pointer Controller 1 Channel 0 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr100;
+
+/** Offset 0x00D8 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr101;
+
+/** Offset 0x00E0 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr110;
+
+/** Offset 0x00E8 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr111;
+
+/** Offset 0x00F0 - Memory SPD Pointer Controller 1 Channel 2 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr120;
+
+/** Offset 0x00F8 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr121;
+
+/** Offset 0x0100 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr130;
+
+/** Offset 0x0108 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1
+ Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
+**/
+ UINT64 MemorySpdPtr131;
+
+/** Offset 0x0110 - RcompResistor settings
+ Indicates RcompResistor settings: Board-dependent
+**/
+ UINT16 RcompResistor;
+
+/** Offset 0x0112 - RcompTarget settings
+ RcompTarget settings: board-dependent
+**/
+ UINT16 RcompTarget[5];
+
+/** Offset 0x011C - LowerBasicMemTestSize feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT8 LowerBasicMemTestSize;
+
+/** Offset 0x011D - Reserved
+**/
+ UINT8 Reserved5[2];
+
+/** Offset 0x011F - CaVrefHigh feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT8 CaVrefHigh;
+
+/** Offset 0x0120 - CsVrefLow feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT8 CsVrefLow;
+
+/** Offset 0x0121 - CsVrefHigh feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT8 CsVrefHigh;
+
+/** Offset 0x0122 - CaVrefLow feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT8 CaVrefLow;
+
+/** Offset 0x0123 - DFETap2StepSize feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT8 DFETap2StepSize;
+
+/** Offset 0x0124 - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT16 Vdd2Mv;
+
+/** Offset 0x0126 - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT16 tWTR_S;
+
+/** Offset 0x0128 - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT16 tCCD_L;
+
+/** Offset 0x012A - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT16 tWTR_L;
+
+/** Offset 0x012C - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT16 tRRD_S;
+
+/** Offset 0x012E - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT16 tRRD_L;
+
+/** Offset 0x0130 - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT16 tRFC4;
+
+/** Offset 0x0132 - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT16 tRFC2;
+
+/** Offset 0x0134 - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT16 tRFCpb;
+
+/** Offset 0x0136 - Reserved
+**/
+ UINT8 Reserved6[7];
+
+/** Offset 0x013D - Vdd2Mv feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT8 LpMode;
+
+/** Offset 0x013E - LowerBasicMemTestSize feature
+ Reduce BasicMemTest size. 0: Disabled (default), regular BasicMemTest. 1: Enabled,
+ shorter BasicMemTest (faster boot)
+ $EN_DIS
+**/
+ UINT8 DFETap1StepSize;
+
+/** Offset 0x013F - Dqs Map CPU to DRAM MC 0 CH 0
+ Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+ UINT8 DqsMapCpu2DramMc0Ch0[2];
+
+/** Offset 0x0141 - Dqs Map CPU to DRAM MC 0 CH 1
+ Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+ UINT8 DqsMapCpu2DramMc0Ch1[2];
+
+/** Offset 0x0143 - Dqs Map CPU to DRAM MC 0 CH 2
+ Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+ UINT8 DqsMapCpu2DramMc0Ch2[2];
+
+/** Offset 0x0145 - Dqs Map CPU to DRAM MC 0 CH 3
+ Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+ UINT8 DqsMapCpu2DramMc0Ch3[2];
+
+/** Offset 0x0147 - Dqs Map CPU to DRAM MC 1 CH 0
+ Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+ UINT8 DqsMapCpu2DramMc1Ch0[2];
+
+/** Offset 0x0149 - Dqs Map CPU to DRAM MC 1 CH 1
+ Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+ UINT8 DqsMapCpu2DramMc1Ch1[2];
+
+/** Offset 0x014B - Dqs Map CPU to DRAM MC 1 CH 2
+ Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+ UINT8 DqsMapCpu2DramMc1Ch2[2];
+
+/** Offset 0x014D - Dqs Map CPU to DRAM MC 1 CH 3
+ Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+ UINT8 DqsMapCpu2DramMc1Ch3[2];
+
+/** Offset 0x014F - Dq Map CPU to DRAM MC 0 CH 0
+ Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+ UINT8 DqMapCpu2DramMc0Ch0[16];
+
+/** Offset 0x015F - Dq Map CPU to DRAM MC 0 CH 1
+ Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+ UINT8 DqMapCpu2DramMc0Ch1[16];
+
+/** Offset 0x016F - Dq Map CPU to DRAM MC 0 CH 2
+ Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+ UINT8 DqMapCpu2DramMc0Ch2[16];
+
+/** Offset 0x017F - Dq Map CPU to DRAM MC 0 CH 3
+ Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+ UINT8 DqMapCpu2DramMc0Ch3[16];
+
+/** Offset 0x018F - Dq Map CPU to DRAM MC 1 CH 0
+ Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent
+**/
+ UINT8 DqMapCpu2DramMc1Ch0[16];
+
+/** Offset 0x019F - Dq Map CPU to DRAM MC 1 CH 1
+ Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent
+**/
+ UINT8 DqMapCpu2DramMc1Ch1[16];
+
+/** Offset 0x01AF - Dq Map CPU to DRAM MC 1 CH 2
+ Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent
+**/
+ UINT8 DqMapCpu2DramMc1Ch2[16];
+
+/** Offset 0x01BF - Dq Map CPU to DRAM MC 1 CH 3
+ Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent
+**/
+ UINT8 DqMapCpu2DramMc1Ch3[16];
+
+/** Offset 0x01CF - Reserved
+**/
+ UINT8 Reserved7[2];
+
+/** Offset 0x01D1 - MRC OCSafeMode
+ OverClocking Safe Mode
+ 0:CMOS, 1:Break, 2:Force
+**/
+ UINT8 OCSafeMode;
+
+/** Offset 0x01D2 - Reserved
+**/
+ UINT8 Reserved8;
+
+/** Offset 0x01D3 - Dqs Pins Interleaved Setting
+ Indicates DqPinsInterleaved setting: board-dependent
+ $EN_DIS
+**/
+ UINT8 DqPinsInterleaved;
+
+/** Offset 0x01D4 - Reserved
+**/
+ UINT8 Reserved9[2];
+
+/** Offset 0x01D6 - MRC Fast Boot
+ Enables/Disable the MRC fast path thru the MRC
+ $EN_DIS
+**/
+ UINT16 MrcFastBoot;
+
+/** Offset 0x01D8 - Rank Margin Tool per Task
+ This option enables the user to execute Rank Margin Tool per major training step
+ in the MRC.
+ $EN_DIS
+**/
+ UINT8 RmtPerTask;
+
+/** Offset 0x01D9 - Training Trace
+ This option enables the trained state tracing feature in MRC. This feature will
+ print out the key training parameters state across major training steps.
+ $EN_DIS
+**/
+ UINT8 TrainTrace;
+
+/** Offset 0x01DA - Probeless Trace
+ Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB.
+ This also requires IED to be enabled.
+ $EN_DIS
+**/
+ UINT8 ProbelessTrace;
+
+/** Offset 0x01DB - Reserved
+**/
+ UINT8 Reserved10;
+
+/** Offset 0x01DC - DDR Frequency Limit
+ Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867,
+ 2133, 2400, 2667, 2933 and 0 for Auto.
+ 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto
+**/
+ UINT16 DdrFreqLimit;
+
+/** Offset 0x01DE - SAGV
+ System Agent dynamic frequency support.
+ 0:Disabled, 1:Enabled
+**/
+ UINT8 SaGv;
+
+/** Offset 0x01DF - SAGV WP Mask
+ System Agent dynamic frequency workpoints that memory will be training at the enabled
+ frequencies.
+ 0x3:Points0_1, 0x7:Points0_1_2, 0xF:AllPoints0_1_2_3
+**/
+ UINT8 SaGvWpMask;
+
+/** Offset 0x01E0 - SAGV Gear Ratio
+ Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+ UINT8 SaGvGear[4];
+
+/** Offset 0x01E4 - SAGV Frequency
+ SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300.
+**/
+ UINT16 SaGvFreq[4];
+
+/** Offset 0x01EC - SAGV Disabled Gear Ratio
+ Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2
+**/
+ UINT8 GearRatio;
+
+/** Offset 0x01ED - Rank Margin Tool
+ Enable/disable Rank Margin Tool.
+ $EN_DIS
+**/
+ UINT8 RMT;
+
+/** Offset 0x01EE - Controller 0 Channel 0 DIMM Control
+ Enable / Disable DIMMs on Controller 0 Channel 0
+ $EN_DIS
+**/
+ UINT8 DisableMc0Ch0;
+
+/** Offset 0x01EF - Controller 0 Channel 1 DIMM Control
+ Enable / Disable DIMMs on Controller 0 Channel 1
+ $EN_DIS
+**/
+ UINT8 DisableMc0Ch1;
+
+/** Offset 0x01F0 - Controller 0 Channel 2 DIMM Control
+ Enable / Disable DIMMs on Controller 0 Channel 2
+ $EN_DIS
+**/
+ UINT8 DisableMc0Ch2;
+
+/** Offset 0x01F1 - Controller 0 Channel 3 DIMM Control
+ Enable / Disable DIMMs on Controller 0 Channel 3
+ $EN_DIS
+**/
+ UINT8 DisableMc0Ch3;
+
+/** Offset 0x01F2 - Controller 1 Channel 0 DIMM Control
+ Enable / Disable DIMMs on Controller 1 Channel 0
+ $EN_DIS
+**/
+ UINT8 DisableMc1Ch0;
+
+/** Offset 0x01F3 - Controller 1 Channel 1 DIMM Control
+ Enable / Disable DIMMs on Controller 1 Channel 1
+ $EN_DIS
+**/
+ UINT8 DisableMc1Ch1;
+
+/** Offset 0x01F4 - Controller 1 Channel 2 DIMM Control
+ Enable / Disable DIMMs on Controller 1 Channel 2
+ $EN_DIS
+**/
+ UINT8 DisableMc1Ch2;
+
+/** Offset 0x01F5 - Controller 1 Channel 3 DIMM Control
+ Enable / Disable DIMMs on Controller 1 Channel 3
+ $EN_DIS
+**/
+ UINT8 DisableMc1Ch3;
+
+/** Offset 0x01F6 - Scrambler Support
+ This option enables data scrambling in memory.
+ $EN_DIS
+**/
+ UINT8 ScramblerSupport;
+
+/** Offset 0x01F7 - Reserved
+**/
+ UINT8 Reserved11[3];
+
+/** Offset 0x01FA - Memory Ratio
+ Automatic or the frequency will equal ratio times reference clock. Set to Auto to
+ recalculate memory timings listed below.
+ 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
+**/
+ UINT16 Ratio;
+
+/** Offset 0x01FC - tCL
+ CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tCL;
+
+/** Offset 0x01FE - tCWL
+ Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tCWL;
+
+/** Offset 0x0200 - tFAW
+ Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tFAW;
+
+/** Offset 0x0202 - SPD Profile Selected
+ Select DIMM timing profile. Options are 0=Default Profile, 1=Custom Profile, 2=XMP
+ Profile 1, 3=XMP Profile 2
+ 0:Default Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2
+**/
+ UINT8 SpdProfileSelected;
+
+/** Offset 0x0203
+**/
+ UINT8 RXVREFPERBIT;
+
+/** Offset 0x0204 - Reserved
+**/
+ UINT8 Reserved12;
+
+/** Offset 0x0205 - Ch Hash Override
+ Select if Channel Hash setting values will be taken from input parameters or automatically
+ taken from POR values depending on DRAM type detected. NOTE: ONLY if Memory interleaved Mode
+ $EN_DIS
+**/
+ UINT8 ChHashOverride;
+
+/** Offset 0x0206 - Reserved
+**/
+ UINT8 Reserved13[2];
+
+/** Offset 0x0208 - DQS Rise/Fall
+ Enables/Disable DQS Rise/Fall
+ $EN_DIS
+**/
+ UINT8 RDDQSODTT;
+
+/** Offset 0x0209 - Reserved
+**/
+ UINT8 Reserved14[2];
+
+/** Offset 0x020B - Functional Duty Cycle Correction for DDR5 CLK
+ Enable/Disable Functional Duty Cycle Correction for DDR5 CLK
+ 0:Disable, 1:Enable
+**/
+ UINT8 FUNCDCCCLK;
+
+/** Offset 0x020C - Functional Duty Cycle Correction for DDR5 DQS
+ Enable/Disable Functional Duty Cycle Correction for DDR5 DQS
+ 0:Disable, 1:Enable
+**/
+ UINT8 FUNCDCCDQS;
+
+/** Offset 0x020D
+**/
+ UINT8 FUNCDCCWCK;
+
+/** Offset 0x020E - Duty Cycle Correction for LP5 DCA
+ Enable/Disable Duty Cycle Correction for LP5 DCA
+ $EN_DIS
+**/
+ UINT8 DCCLP5WCKDCA;
+
+/** Offset 0x020F - Reserved
+**/
+ UINT8 Reserved15;
+
+/** Offset 0x0210 - DQ/DQS Swizzle Training
+ Enable/Disable DQ/DQS Swizzle Training
+ $EN_DIS
+**/
+ UINT32 DQDQSSWZ;
+
+/** Offset 0x0214 - Reserved
+**/
+ UINT8 Reserved16[4];
+
+/** Offset 0x0218 - Functional Duty Cycle Correction for Data DQ
+ Enable/Disable Functional Duty Cycle Correction for Data DQ
+ 0:Disable, 1:Enable
+**/
+ UINT8 FUNCDCCDQ;
+
+/** Offset 0x0219 - Reserved
+**/
+ UINT8 Reserved17[5];
+
+/** Offset 0x021E - tRAS
+ RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tRAS;
+
+/** Offset 0x0220 - tRCD/tRP
+ RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used
+ if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+ UINT16 tRCDtRP;
+
+/** Offset 0x0222 - Reserved
+**/
+ UINT8 Reserved18[2];
+
+/** Offset 0x0224 - tREFI
+ Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT32 tREFI;
+
+/** Offset 0x0228 - Unmatched Rx Calibration
+ Enable/Disable Rx Unmatched Calibration
+ $EN_DIS
+**/
+ UINT32 RXUNMATCHEDCAL;
+
+/** Offset 0x022C - Hard Post Package Repair
+ Enables/Disable Hard Post Package Repair
+ $EN_DIS
+**/
+ UINT32 PPR;
+
+/** Offset 0x0230 - Reserved
+**/
+ UINT8 Reserved19;
+
+/** Offset 0x0231 - PPR Run Once
+ When Eanble, PPR will run only once and then is disabled at next training cycle
+ $EN_DIS
+**/
+ UINT8 PprRunOnce;
+
+/** Offset 0x0232 - PPR Run During Fastboot
+ When Eanble, PPR will run during fastboot
+ $EN_DIS
+**/
+ UINT8 PprRunAtFastboot;
+
+/** Offset 0x0233 - PPR Repair Type
+ PPR Repair Type: 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+ 0:Do not Repair (Default), 1:Soft Repair, 2:Hard Repair
+**/
+ UINT8 PprRepairType;
+
+/** Offset 0x0234 - PPR Error Injection
+ When Eanble, PPR will inject bad rows during testing
+ $EN_DIS
+**/
+ UINT8 PprErrorInjection;
+
+/** Offset 0x0235 - PPR Repair Controller
+ PPR repair controller: User chooses to force repair specifc address
+**/
+ UINT8 PprRepairController;
+
+/** Offset 0x0236 - PPR Repair Channel
+ PPR repair Channel: User chooses to force repair specifc address
+**/
+ UINT8 PprRepairChannel;
+
+/** Offset 0x0237 - PPR Repair Dimm
+ PPR repair Dimm: User chooses to force repair specifc address
+**/
+ UINT8 PprRepairDimm;
+
+/** Offset 0x0238 - PPR Repair Rank
+ PPR repair Rank: User chooses to force repair specifc address
+**/
+ UINT8 PprRepairRank;
+
+/** Offset 0x0239 - Reserved
+**/
+ UINT8 Reserved20[3];
+
+/** Offset 0x023C - PPR Repair Row
+ PPR repair Row: User chooses to force repair specifc address
+**/
+ UINT32 PprRepairRow;
+
+/** Offset 0x0240 - Reserved
+**/
+ UINT8 Reserved21[8];
+
+/** Offset 0x0248 - PPR Repair BankGroup
+ PPR repair BankGroup: User chooses to force repair specifc address
+**/
+ UINT8 PprRepairBankGroup;
+
+/** Offset 0x0249 - Reserved
+**/
+ UINT8 Reserved22;
+
+/** Offset 0x024A - PPR Repair BankGroup
+ PPR repair BankGroup: User chooses to force repair specifc address
+**/
+ UINT16 tCCD_L_WR;
+
+/** Offset 0x024C - LVR Auto Trim
+ Enable/disable LVR Auto Trim
+ $EN_DIS
+**/
+ UINT32 LVRAUTOTRIM;
+
+/** Offset 0x0250 - Power Saving Meter Update
+ Enable/Disable Power Saving Meter Update
+ $EN_DIS
+**/
+ UINT32 PWRMETER;
+
+/** Offset 0x0254 - Compensation Optimization
+ Enable/Disable Compensation Optimization
+ $EN_DIS
+**/
+ UINT32 OPTIMIZECOMP;
+
+/** Offset 0x0258 - Write DQ/DQS Retraining
+ Enable/Disable Write DQ/DQS Retraining
+ $EN_DIS
+**/
+ UINT32 WRTRETRAIN;
+
+/** Offset 0x025C - Pre-Training Comp Calibration
+ Enable/Disable Pre-Training Comp Calibration
+ $EN_DIS
+**/
+ UINT32 DDRPRECOMP;
+
+/** Offset 0x0260 - Reserved
+**/
+ UINT8 Reserved23[12];
+
+/** Offset 0x026C - DCC Phase Clk Calibration
+ Enable/disable DCC Phase Clk Calibration
+ $EN_DIS
+**/
+ UINT32 RDDQODTT;
+
+/** Offset 0x0270 - RDCTLET
+ Enable/disable Read CTLE Training
+ $EN_DIS
+**/
+ UINT32 RDCTLET;
+
+/** Offset 0x0274 - EMPHASIS
+ Enable/disable DCC Tline Clk Calibration
+ $EN_DIS
+**/
+ UINT8 EMPHASIS;
+
+/** Offset 0x0275 - Reserved
+**/
+ UINT8 Reserved24;
+
+/** Offset 0x0276 - tRFC
+ Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tRFC;
+
+/** Offset 0x0278 - tRRD
+ Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tRRD;
+
+/** Offset 0x027A - tRTP
+ Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used
+ if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+**/
+ UINT16 tRTP;
+
+/** Offset 0x027C - tWR
+ Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
+ 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
+ 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
+ 34:34, 40:40
+**/
+ UINT16 tWR;
+
+/** Offset 0x027E - tWTR
+ Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
+ == 1 (Custom Profile).
+**/
+ UINT16 tWTR;
+
+/** Offset 0x0280 - NMode
+ System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
+**/
+ UINT8 NModeSupport;
+
+/** Offset 0x0281 - LPDDR ODT RttWr
+ Initial RttWr for LP4/5 in Ohms. 0x0 - Auto
+**/
+ UINT8 LpddrRttWr;
+
+/** Offset 0x0282 - Retrain on Fast flow Failure
+ Restart MRC in Cold mode if SW MemTest fails during Fast flow.
+ $EN_DIS
+**/
+ UINT8 RetrainOnFastFail;
+
+/** Offset 0x0283 - LPDDR ODT RttCa
+ Initial RttCa for LP4/5 in Ohms. 0x0 - Auto
+**/
+ UINT8 LpddrRttCa;
+
+/** Offset 0x0284 - DIMM DFE Training
+ Enable/Disable DIMM DFE Training
+ $EN_DIS
+**/
+ UINT8 WRTDIMMDFE;
+
+/** Offset 0x0285 - DDR5 ODT Timing Config
+ Enable/Disable DDR5 ODT TIMING CONFIG
+ $EN_DIS
+**/
+ UINT8 DDR5ODTTIMING;
+
+/** Offset 0x0286 - HobBufferSize
+ Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
+ total HOB size).
+ 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
+**/
+ UINT8 HobBufferSize;
+
+/** Offset 0x0287 - Early Command Training
+ Enables/Disable Early Command Training
+ $EN_DIS
+**/
+ UINT8 ECT;
+
+/** Offset 0x0288 - SenseAmp Offset Training
+ Enables/Disable SenseAmp Offset Training
+ $EN_DIS
+**/
+ UINT8 SOT;
+
+/** Offset 0x0289 - Early ReadMPR Timing Centering 2D
+ Enables/Disable Early ReadMPR Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDMPRTC2D;
+
+/** Offset 0x028A - Read MPR Training
+ Enables/Disable Read MPR Training
+ $EN_DIS
+**/
+ UINT8 RDMPRT;
+
+/** Offset 0x028B - Receive Enable Training
+ Enables/Disable Receive Enable Training
+ $EN_DIS
+**/
+ UINT8 RCVET;
+
+/** Offset 0x028C - Jedec Write Leveling
+ Enables/Disable Jedec Write Leveling
+ $EN_DIS
+**/
+ UINT8 JWRL;
+
+/** Offset 0x028D - Early Write Time Centering 2D
+ Enables/Disable Early Write Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 EWRTC2D;
+
+/** Offset 0x028E - Early Read Time Centering 2D
+ Enables/Disable Early Read Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 ERDTC2D;
+
+/** Offset 0x028F - Early Read Time Centering 2D
+ Enables/Disable Early Read Time Centering 2D
+ $EN_DIS
+**/
+ UINT8 UNMATCHEDWRTC1D;
+
+/** Offset 0x0290 - Write Timing Centering 1D
+ Enables/Disable Write Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRTC1D;
+
+/** Offset 0x0291 - Write Voltage Centering 1D
+ Enables/Disable Write Voltage Centering 1D
+ $EN_DIS
+**/
+ UINT8 WRVC1D;
+
+/** Offset 0x0292 - Read Timing Centering 1D
+ Enables/Disable Read Timing Centering 1D
+ $EN_DIS
+**/
+ UINT8 RDTC1D;
+
+/** Offset 0x0293 - Dimm ODT Training
+ Enables/Disable Dimm ODT Training
+ $EN_DIS
+**/
+ UINT8 DIMMODTT;
+
+/** Offset 0x0294 - DIMM RON Training
+ Enables/Disable DIMM RON Training
+ $EN_DIS
+**/
+ UINT8 DIMMRONT;
+
+/** Offset 0x0295 - Write Drive Strength/Equalization 2D
+ Enables/Disable Write Drive Strength/Equalization 2D
+ $EN_DIS
+**/
+ UINT8 WRDSEQT;
+
+/** Offset 0x0296 - Read Equalization Training
+ Enables/Disable Read Equalization Training
+ $EN_DIS
+**/
+ UINT8 RDEQT;
+
+/** Offset 0x0297 - Write Timing Centering 2D
+ Enables/Disable Write Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRTC2D;
+
+/** Offset 0x0298 - Read Timing Centering 2D
+ Enables/Disable Read Timing Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDTC2D;
+
+/** Offset 0x0299 - Write Voltage Centering 2D
+ Enables/Disable Write Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 WRVC2D;
+
+/** Offset 0x029A - Read Voltage Centering 2D
+ Enables/Disable Read Voltage Centering 2D
+ $EN_DIS
+**/
+ UINT8 RDVC2D;
+
+/** Offset 0x029B - Command Voltage Centering
+ Enables/Disable Command Voltage Centering
+ $EN_DIS
+**/
+ UINT8 CMDVC;
+
+/** Offset 0x029C - Late Command Training
+ Enables/Disable Late Command Training
+ $EN_DIS
+**/
+ UINT8 LCT;
+
+/** Offset 0x029D - Round Trip Latency Training
+ Enables/Disable Round Trip Latency Training
+ $EN_DIS
+**/
+ UINT8 RTL;
+
+/** Offset 0x029E - Turn Around Timing Training
+ Enables/Disable Turn Around Timing Training
+ $EN_DIS
+**/
+ UINT8 TAT;
+
+/** Offset 0x029F - Reserved
+**/
+ UINT8 Reserved25;
+
+/** Offset 0x02A0 - DIMM SPD Alias Test
+ Enables/Disable DIMM SPD Alias Test
+ $EN_DIS
+**/
+ UINT8 ALIASCHK;
+
+/** Offset 0x02A1 - Receive Enable Centering 1D
+ Enables/Disable Receive Enable Centering 1D
+ $EN_DIS
+**/
+ UINT8 RCVENC1D;
+
+/** Offset 0x02A2 - Retrain Margin Check
+ Enables/Disable Retrain Margin Check
+ $EN_DIS
+**/
+ UINT8 RMC;
+
+/** Offset 0x02A3 - ECC Support
+ Enables/Disable ECC Support
+ $EN_DIS
+**/
+ UINT8 EccSupport;
+
+/** Offset 0x02A4 - Reserved
+**/
+ UINT8 Reserved26[2];
+
+/** Offset 0x02A6 - Ibecc
+ In-Band ECC Support
+ $EN_DIS
+**/
+ UINT8 Ibecc;
+
+/** Offset 0x02A7 - IbeccParity
+ In-Band ECC Parity Control
+ $EN_DIS
+**/
+ UINT8 IbeccParity;
+
+/** Offset 0x02A8 - Reserved
+**/
+ UINT8 Reserved27[4];
+
+/** Offset 0x02AC - IbeccOperationMode
+ In-Band ECC Operation Mode
+ 0:Protect base on address range, 1: Non-protected, 2: All protected
+**/
+ UINT8 IbeccOperationMode;
+
+/** Offset 0x02AD - IbeccProtectedRegionEnable
+ In-Band ECC Protected Region Enable
+ $EN_DIS
+**/
+ UINT8 IbeccProtectedRegionEnable[8];
+
+/** Offset 0x02B5 - Reserved
+**/
+ UINT8 Reserved28;
+
+/** Offset 0x02B6 - IbeccProtectedRegionBases
+ IBECC Protected Region Bases per IBECC instance
+**/
+ UINT16 IbeccProtectedRegionBase[8];
+
+/** Offset 0x02C6 - IbeccProtectedRegionMasks
+ IBECC Protected Region Masks
+**/
+ UINT16 IbeccProtectedRegionMask[8];
+
+/** Offset 0x02D6 - Memory Remap
+ Enables/Disable Memory Remap
+ $EN_DIS
+**/
+ UINT8 RemapEnable;
+
+/** Offset 0x02D7 - Reserved
+**/
+ UINT8 Reserved29;
+
+/** Offset 0x02D8 - Rank Interleave support
+ Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
+ the same time.
+ $EN_DIS
+**/
+ UINT32 RankInterleave;
+
+/** Offset 0x02DC - Enhanced Interleave support
+ Enables/Disable Enhanced Interleave support
+ $EN_DIS
+**/
+ UINT32 EnhancedInterleave;
+
+/** Offset 0x02E0 - Ch Hash Support
+ Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
+ $EN_DIS
+**/
+ UINT32 ChHashEnable;
+
+/** Offset 0x02E4 - DDR PowerDown and idle counter
+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT32 EnablePwrDn;
+
+/** Offset 0x02E8 - DDR PowerDown and idle counter
+ Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 EnablePwrDnLpddr;
+
+/** Offset 0x02E9 - Reserved
+**/
+ UINT8 Reserved30[3];
+
+/** Offset 0x02EC - SelfRefresh Enable
+ Enables/Disable SelfRefresh Enable
+ $EN_DIS
+**/
+ UINT32 SrefCfgEna;
+
+/** Offset 0x02F0 - Throttler CKEMin Defeature
+ Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
+ $EN_DIS
+**/
+ UINT8 ThrtCkeMinDefeatLpddr;
+
+/** Offset 0x02F1 - Reserved
+**/
+ UINT8 Reserved31[3];
+
+/** Offset 0x02F4 - Throttler CKEMin Defeature
+ Enables/Disable Throttler CKEMin Defeature
+ $EN_DIS
+**/
+ UINT32 ThrtCkeMinDefeat;
+
+/** Offset 0x02F8 - Exit On Failure (MRC)
+ Enables/Disable Exit On Failure (MRC)
+ $EN_DIS
+**/
+ UINT8 ExitOnFailure;
+
+/** Offset 0x02F9 - Reserved
+**/
+ UINT8 Reserved32[2];
+
+/** Offset 0x02FB - Read Voltage Centering 1D
+ Enable/Disable Read Voltage Centering 1D
+ $EN_DIS
+**/
+ UINT8 RDVC1D;
+
+/** Offset 0x02FC - TxDqTCO Comp Training
+ Enable/Disable TxDqTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 TXTCO;
+
+/** Offset 0x02FD - ClkTCO Comp Training
+ Enable/Disable ClkTCO Comp Training
+ $EN_DIS
+**/
+ UINT8 CLKTCO;
+
+/** Offset 0x02FE - CMD Slew Rate Training
+ Enable/Disable CMD Slew Rate Training
+ $EN_DIS
+**/
+ UINT8 CMDSR;
+
+/** Offset 0x02FF - CMD Drive Strength and Tx Equalization
+ Enable/Disable CMD Drive Strength and Tx Equalization
+ $EN_DIS
+**/
+ UINT8 CMDDSEQ;
+
+/** Offset 0x0300 - DIMM CA ODT Training
+ Enable/Disable DIMM CA ODT Training
+ $EN_DIS
+**/
+ UINT8 DIMMODTCA;
+
+/** Offset 0x0301 - Read Vref Decap Training*
+ Enable/Disable Read Vref Decap Training*
+ $EN_DIS
+**/
+ UINT8 RDVREFDC;
+
+/** Offset 0x0302 - Vddq Training
+ Enable/Disable Vddq Training
+ $EN_DIS
+**/
+ UINT8 VDDQT;
+
+/** Offset 0x0303 - Rank Margin Tool Per Bit
+ Enable/Disable Rank Margin Tool Per Bit
+ $EN_DIS
+**/
+ UINT8 RMTBIT;
+
+/** Offset 0x0304 - Ref PI Calibration
+ Enable/Disable Ref PI Calibration
+ $EN_DIS
+**/
+ UINT8 REFPI;
+
+/** Offset 0x0305 - VccClk FF Offset Correction
+ Enable/Disable VccClk FF Offset Correction
+ 0:Disable, 1:Enable
+**/
+ UINT8 VCCCLKFF;
+
+/** Offset 0x0306 - Reserved
+**/
+ UINT8 Reserved33[2];
+
+/** Offset 0x0308 - Data PI Linearity Calibration
+ Enable/Disable {Data PI Linearity Calibration
+ $EN_DIS
+**/
+ UINT32 DATAPILIN;
+
+/** Offset 0x030C - Ddr5 Rx Cross-Talk Cancellation
+ Enable/Disable {Ddr5 Rx Cross-Talk Cancellation
+ $EN_DIS
+**/
+ UINT8 DDR5XTALK;
+
+/** Offset 0x030D - Retrain On Working Channel
+ Enables/Disable Retrain On Working Channel feature
+ $EN_DIS
+**/
+ UINT8 RetrainToWorkingChannel;
+
+/** Offset 0x030E - Reserved
+**/
+ UINT8 Reserved34;
+
+/** Offset 0x030F - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+ $EN_DIS
+**/
+ UINT8 IsDdr5MR7WicaSupported;
+
+/** Offset 0x0310 - Ch Hash Interleaved Bit
+ Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
+ the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
+ 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
+**/
+ UINT8 ChHashInterleaveBit;
+
+/** Offset 0x0311 - Reserved
+**/
+ UINT8 Reserved35;
+
+/** Offset 0x0312 - Ch Hash Mask
+ Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
+ BITS [19:6] Default is 0x30CC
+**/
+ UINT16 ChHashMask;
+
+/** Offset 0x0314 - Reserved
+**/
+ UINT8 Reserved36[2];
+
+/** Offset 0x0316 - Throttler CKEMin Timer
+ Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
+ Dfault is 0x00
+**/
+ UINT8 ThrtCkeMinTmr;
+
+/** Offset 0x0317 - Allow Opp Ref Below Write Threhold
+ Allow opportunistic refreshes while we don't exit power down.
+ $EN_DIS
+**/
+ UINT8 AllowOppRefBelowWriteThrehold;
+
+/** Offset 0x0318 - Write Threshold
+ Number of writes that can be accumulated while CKE is low before CKE is asserted.
+**/
+ UINT8 WriteThreshold;
+
+/** Offset 0x0319 - MC_REFRESH_RATE
+ Type of Refresh Rate used to prevent Row Hammer. Default is NORMAL Refresh
+ 0:NORMAL Refresh, 1:1x Refresh, 2:2x Refresh, 3:4x Refresh
+**/
+ UINT8 McRefreshRate;
+
+/** Offset 0x031A - Refresh Watermarks
+ Refresh Watermarks: 0-Low, 1-High (default)
+ 0:Set Refresh Watermarks to Low, 1:Set Refresh Watermarks to High (Default)
+**/
+ UINT8 RefreshWm;
+
+/** Offset 0x031B - Reserved
+**/
+ UINT8 Reserved37[2];
+
+/** Offset 0x031D - Power Down Mode
+ This option controls command bus tristating during idle periods
+ 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
+**/
+ UINT8 PowerDownMode;
+
+/** Offset 0x031E - Pwr Down Idle Timer
+ The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
+ AUTO: 64 for ULX/ULT, 128 for DT/Halo
+**/
+ UINT8 PwdwnIdleCounter;
+
+/** Offset 0x031F - Page Close Idle Timeout
+ This option controls Page Close Idle Timeout
+ 0:Enabled, 1:Disabled
+**/
+ UINT8 DisPgCloseIdleTimeout;
+
+/** Offset 0x0320 - Reserved
+**/
+ UINT8 Reserved38;
+
+/** Offset 0x0321 - MRC Safe Mode Override
+ SafeModeOverride[0] Enable DdrSafeMode override, SafeModeOverride[1] Enable McSafeMode
+ override, SafeModeOverride[2] Enable MrcSafeMode override, SafeModeOverride[3]
+ Enable Training Algorithm (TrainingEnables) safe mode override, SafeModeOverride[4]
+ Enable SaGv safe mode override
+**/
+ UINT8 SafeModeOverride;
+
+/** Offset 0x0322 - Reserved
+**/
+ UINT8 Reserved39[2];
+
+/** Offset 0x0324 - DDR Phy Safe Mode Support
+ DdrSafeMode[0]: Basic PM Features, DdrSafeMode[1]: Spine Gating, DdrSafeMode[2]:
+ Advanced DCC, DdrSafeMode[3]: R2R Training, DdrSafeMode[4]: Transformer Mode, DdrSafeMode[5]:
+ PLL Operation, DdrSafeMode[6]: Safe ODT
+**/
+ UINT32 DdrSafeMode;
+
+/** Offset 0x0328 - Mc Safe Mode Support
+ McSafeMode[0]: Clk Gate / BGF, McSafeMode[1]: CKE Pdwn, McSafeMode[2]: Tristate,
+ McSafeMode[3]: PHY Power States / Clock Spine, McSafeMode[4]: Same Rank TA, McSafeMode[5]:
+ Different Rank TA, McSafeMode[6]: MR4_Period / ZQCAL_Period McSafeMode[7]: LP5
+ Wck Mode, SafeMode[8]: Self Refresh, McSafeMode[9]: WR/RD Retraining, McSafeMode[10]:
+ Power Saving
+**/
+ UINT8 McSafeMode;
+
+/** Offset 0x0329 - Ask MRC to clear memory content
+ Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
+ $EN_DIS
+**/
+ UINT8 CleanMemory;
+
+/** Offset 0x032A - Reserved
+**/
+ UINT8 Reserved40[8];
+
+/** Offset 0x0332 - RMTLoopCount
+ Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
+**/
+ UINT8 RMTLoopCount;
+
+/** Offset 0x0333 - DdrOneDpc
+ DDR 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only,
+ or on both (default)
+ 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled
+**/
+ UINT8 DdrOneDpc;
+
+/** Offset 0x0334 - Vddq Voltage Override
+ # is multiple of 1mV where 0 means Auto.
+**/
+ UINT16 VddqVoltageOverride;
+
+/** Offset 0x0336 - VccIog Voltage Override
+ # is multiple of 1mV where 0 means Auto.
+**/
+ UINT16 VccIogVoltageOverride;
+
+/** Offset 0x0338 - VccClk Voltage Override
+ # is multiple of 1mV where 0 means Auto.
+**/
+ UINT16 VccClkVoltageOverride;
+
+/** Offset 0x033A - ThrtCkeMinTmrLpddr
+ Throttler CKE min timer for LPDDR: 0=Minimal, 0xFF=Maximum, <b>0x00=Default</b>
+**/
+ UINT8 ThrtCkeMinTmrLpddr;
+
+/** Offset 0x033B - Reserved
+**/
+ UINT8 Reserved41;
+
+/** Offset 0x033C - VccClk Voltage Override
+ # is multiple of 1mV where 0 means Auto.
+**/
+ UINT16 MarginLimitL2;
+
+/** Offset 0x033E - Extended Bank Hashing
+ Eanble/Disable ExtendedBankHashing
+ $EN_DIS
+**/
+ UINT8 ExtendedBankHashing;
+
+/** Offset 0x033F - Reserved
+**/
+ UINT8 Reserved42;
+
+/** Offset 0x0340 - Command Pins Mapping
+ BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
+ 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
+**/
+ UINT8 Lp5CccConfig;
+
+/** Offset 0x0341 - Command Pins Mirrored
+ BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
+ 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
+**/
+ UINT8 CmdMirror;
+
+/** Offset 0x0342 - Time Measure
+ Time Measure: 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 MrcTimeMeasure;
+
+/** Offset 0x0343 - Reserved
+**/
+ UINT8 Reserved43[8];
+
+/** Offset 0x034B - Board Type
+ MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
+ Halo, 7=UP Server
+ 0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
+**/
+ UINT8 UserBd;
+
+/** Offset 0x034C - Spd Address Table
+ Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
+ if SPD Address is 00
+**/
+ UINT8 SpdAddressTable[16];
+
+/** Offset 0x035C - Enable/Disable MRC TXT dependency
+ When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
+ MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
+ $EN_DIS
+**/
+ UINT8 TxtImplemented;
+
+/** Offset 0x035D - Reserved
+**/
+ UINT8 Reserved44;
+
+/** Offset 0x035E - Skip external display device scanning
+ Enable: Do not scan for external display device, Disable (Default): Scan external
+ display devices
+ $EN_DIS
+**/
+ UINT8 SkipExtGfxScan;
+
+/** Offset 0x035F - Generate BIOS Data ACPI Table
+ Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
+ $EN_DIS
+**/
+ UINT8 BdatEnable;
+
+/** Offset 0x0360 - BdatTestType
+ Indicates the type of Memory Training data to populate into the BDAT ACPI table.
+ 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
+**/
+ UINT8 BdatTestType;
+
+/** Offset 0x0361 - Enable PCH HSIO PCIE Rx Set Ctle
+ Enable PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtleEnable[28];
+
+/** Offset 0x037D - PCH HSIO PCIE Rx Set Ctle Value
+ PCH PCIe Gen 3 Set CTLE Value.
+**/
+ UINT8 PchPcieHsioRxSetCtle[28];
+
+/** Offset 0x0399 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28];
+
+/** Offset 0x03B5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen1DownscaleAmp[28];
+
+/** Offset 0x03D1 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28];
+
+/** Offset 0x03ED - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen2DownscaleAmp[28];
+
+/** Offset 0x0409 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28];
+
+/** Offset 0x0425 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+ PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
+**/
+ UINT8 PchPcieHsioTxGen3DownscaleAmp[28];
+
+/** Offset 0x0441 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen1DeEmphEnable[28];
+
+/** Offset 0x045D - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+ PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen1DeEmph[28];
+
+/** Offset 0x0479 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28];
+
+/** Offset 0x0495 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+ PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph3p5[28];
+
+/** Offset 0x04B1 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28];
+
+/** Offset 0x04CD - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+ PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
+**/
+ UINT8 PchPcieHsioTxGen2DeEmph6p0[28];
+
+/** Offset 0x04E9 - HD Audio DMIC Link Clock Select
+ Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB
+ 0: Both, 1: ClkA, 2: ClkB
+**/
+ UINT8 PchHdaAudioLinkDmicClockSelect[2];
+
+/** Offset 0x04EB - Enable Intel HD Audio (Azalia)
+ 0: Disable, 1: Enable (Default) Azalia controller
+ $EN_DIS
+**/
+ UINT8 PchHdaEnable;
+
+/** Offset 0x04EC - Universal Audio Architecture compliance for DSP enabled system
+ 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
+ driver or SST driver supported).
+ $EN_DIS
+**/
+ UINT8 PchHdaDspUaaCompliance;
+
+/** Offset 0x04ED - Enable HD Audio Link
+ Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
+ $EN_DIS
+**/
+ UINT8 PchHdaAudioLinkHdaEnable;
+
+/** Offset 0x04EE - Enable HDA SDI lanes
+ Enable/disable HDA SDI lanes.
+**/
+ UINT8 PchHdaSdiEnable[2];
+
+/** Offset 0x04F0 - Enable HD Audio DMIC_N Link
+ Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
+**/
+ UINT8 PchHdaAudioLinkDmicEnable[2];
+
+/** Offset 0x04F2 - Reserved
+**/
+ UINT8 Reserved45[2];
+
+/** Offset 0x04F4 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+ Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
+**/
+ UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
+
+/** Offset 0x04FC - Enable HD Audio DSP
+ Enable/disable HD Audio DSP feature.
+ $EN_DIS
+**/
+ UINT8 PchHdaDspEnable;
+
+/** Offset 0x04FD - Reserved
+**/
+ UINT8 Reserved46[3];
+
+/** Offset 0x0500 - DMIC<N> Data Pin Muxing
+ Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
+**/
+ UINT32 PchHdaAudioLinkDmicDataPinMux[2];
+
+/** Offset 0x0508 - Enable HD Audio SSP0 Link
+ Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
+**/
+ UINT8 PchHdaAudioLinkSspEnable[7];
+
+/** Offset 0x050F - Reserved
+**/
+ UINT8 Reserved47[117];
+
+/** Offset 0x0584 - Enable HD Audio SoundWire#N Link
+ Enable/disable HD Audio SNDW#N link. Muxed with HDA.
+**/
+ UINT8 PchHdaAudioLinkSndwEnable[5];
+
+/** Offset 0x0589 - iDisp-Link Frequency
+ iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
+ 4: 96MHz, 3: 48MHz
+**/
+ UINT8 PchHdaIDispLinkFrequency;
+
+/** Offset 0x058A - iDisp-Link T-mode
+ iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
+ 0: 2T, 2: 4T, 3: 8T, 4: 16T
+**/
+ UINT8 PchHdaIDispLinkTmode;
+
+/** Offset 0x058B - Reserved
+**/
+ UINT8 Reserved48[45];
+
+/** Offset 0x05B8 - iDisplay Audio Codec disconnection
+ 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
+ $EN_DIS
+**/
+ UINT8 PchHdaIDispCodecDisconnect;
+
+/** Offset 0x05B9 - Reserved
+**/
+ UINT8 Reserved49[5];
+
+/** Offset 0x05BE - HDA Power/Clock Gating (PGD/CGD)
+ Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
+ FORCE_ENABLE, 2: FORCE_DISABLE.
+ 0: POR, 1: Force Enable, 2: Force Disable
+**/
+ UINT8 PchHdaTestPowerClockGating;
+
+/** Offset 0x05BF - Reserved
+**/
+ UINT8 Reserved50[5];
+
+/** Offset 0x05C4 - Usage type for ClkSrc
+ 0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
+**/
+ UINT8 PcieClkSrcUsage[18];
+
+/** Offset 0x05D6 - ClkReq-to-ClkSrc mapping
+ Number of ClkReq signal assigned to ClkSrc
+**/
+ UINT8 PcieClkSrcClkReq[18];
+
+/** Offset 0x05E8 - Reserved
+**/
+ UINT8 Reserved51[48];
+
+/** Offset 0x0618 - Enable PCIE RP Mask
+ Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
+ for port1, bit1 for port2, and so on.
+**/
+ UINT32 PcieRpEnableMask;
+
+/** Offset 0x061C - Debug Interfaces
+ Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
+ BIT2 - Not used.
+**/
+ UINT8 PcdDebugInterfaceFlags;
+
+/** Offset 0x061D - Reserved
+**/
+ UINT8 Reserved52[3];
+
+/** Offset 0x0620 - Serial Io Uart Debug Mmio Base
+ Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
+ = SerialIoUartPci.
+**/
+ UINT32 SerialIoUartDebugMmioBase;
+
+/** Offset 0x0624 - PcdSerialDebugLevel
+ Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 PcdSerialDebugLevel;
+
+/** Offset 0x0625 - SerialDebugMrcLevel
+ MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
+ Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
+ Info & Verbose.
+ 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load
+ Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose
+**/
+ UINT8 SerialDebugMrcLevel;
+
+/** Offset 0x0626 - Serial Io Uart Debug Controller Number
+ Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
+ Core interface, it cannot be used for debug purpose.
+ 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
+**/
+ UINT8 SerialIoUartDebugControllerNumber;
+
+/** Offset 0x0627 - Serial Io Uart Debug Parity
+ Set default Parity.
+ 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 SerialIoUartDebugParity;
+
+/** Offset 0x0628 - Serial Io Uart Debug BaudRate
+ Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
+ 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
+**/
+ UINT32 SerialIoUartDebugBaudRate;
+
+/** Offset 0x062C - Serial Io Uart Debug Stop Bits
+ Set default stop bits.
+ 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
+**/
+ UINT8 SerialIoUartDebugStopBits;
+
+/** Offset 0x062D - Serial Io Uart Debug Data Bits
+ Set default word length. 0: Default, 5,6,7,8
+ 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
+**/
+ UINT8 SerialIoUartDebugDataBits;
+
+/** Offset 0x062E - Enable/Disable SA IPU
+ Enable(Default): Enable SA IPU, Disable: Disable SA IPU
+ $EN_DIS
+**/
+ UINT8 ImguClkOutEn[6];
+
+/** Offset 0x0634 - Enable/Disable SA IPU
+ Enable(Default): Enable SA IPU, Disable: Disable SA IPU
+ $EN_DIS
+**/
+ UINT8 SaIpuEnable;
+
+/** Offset 0x0635 - Disable and Lock Watch Dog Register
+ Set 1 to clear WDT status, then disable and lock WDT registers.
+ $EN_DIS
+**/
+ UINT8 WdtDisableAndLock;
+
+/** Offset 0x0636 - Reserved
+**/
+ UINT8 Reserved53[6];
+
+/** Offset 0x063C - HECI Timeouts
+ 0: Disable, 1: Enable (Default) timeout check for HECI
+ $EN_DIS
+**/
+ UINT8 HeciTimeouts;
+
+/** Offset 0x063D - HECI2 Interface Communication
+ Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
+ $EN_DIS
+**/
+ UINT8 HeciCommunication2;
+
+/** Offset 0x063E - Check HECI message before send
+ Test, 0: disable, 1: enable, Enable/Disable message check.
+ $EN_DIS
+**/
+ UINT8 DisableMessageCheck;
+
+/** Offset 0x063F - Force ME DID Init Status
+ Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
+ ME DID init stat value
+ $EN_DIS
+**/
+ UINT8 DidInitStat;
+
+/** Offset 0x0640 - Enable KT device
+ Test, 0: POR, 1: enable, 2: disable, Enable or Disable KT device.
+ $EN_DIS
+**/
+ UINT8 KtDeviceEnable;
+
+/** Offset 0x0641 - CPU Replaced Polling Disable
+ Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
+ $EN_DIS
+**/
+ UINT8 DisableCpuReplacedPolling;
+
+/** Offset 0x0642 - Skip CPU replacement check
+ Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
+ $EN_DIS
+**/
+ UINT8 SkipCpuReplacementCheck;
+
+/** Offset 0x0643 - Skip MBP HOB
+ Test, 0: disable, 1: enable, Enable/Disable sending MBP message and creating MBP Hob.
+ $EN_DIS
+**/
+ UINT8 SkipMbpHob;
+
+/** Offset 0x0644 - Reserved
+**/
+ UINT8 Reserved54[2];
+
+/** Offset 0x0646 - ISA Serial Base selection
+ Select ISA Serial Base address. Default is 0x3F8.
+ 0:0x3F8, 1:0x2F8
+**/
+ UINT8 PcdIsaSerialUartBase;
+
+/** Offset 0x0647 - PcdSerialDebugBaudRate
+ Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
+ 3:9600, 4:19200, 6:56700, 7:115200
+**/
+ UINT8 PcdSerialDebugBaudRate;
+
+/** Offset 0x0648 - Post Code Output Port
+ This option configures Post Code Output Port
+**/
+ UINT16 PostCodeOutputPort;
+
+/** Offset 0x064A - Reserved
+**/
+ UINT8 Reserved55[26];
+
+/** Offset 0x0664 - Enable SMBus
+ Enable/disable SMBus controller.
+ $EN_DIS
+**/
+ UINT8 SmbusEnable;
+
+/** Offset 0x0665 - Enable SMBus ARP support
+ Enable SMBus ARP support.
+ $EN_DIS
+**/
+ UINT8 SmbusArpEnable;
+
+/** Offset 0x0666 - Number of RsvdSmbusAddressTable.
+ The number of elements in the RsvdSmbusAddressTable.
+**/
+ UINT8 PchNumRsvdSmbusAddresses;
+
+/** Offset 0x0667 - Reserved
+**/
+ UINT8 Reserved56;
+
+/** Offset 0x0668 - SMBUS Base Address
+ SMBUS Base Address (IO space).
+**/
+ UINT16 PchSmbusIoBase;
+
+/** Offset 0x066A - Enable SMBus Alert Pin
+ Enable SMBus Alert Pin.
+ $EN_DIS
+**/
+ UINT8 PchSmbAlertEnable;
+
+/** Offset 0x066B - Reserved
+**/
+ UINT8 Reserved57[13];
+
+/** Offset 0x0678 - Smbus dynamic power gating
+ Disable or Enable Smbus dynamic power gating.
+ $EN_DIS
+**/
+ UINT8 SmbusDynamicPowerGating;
+
+/** Offset 0x0679 - SMBUS SPD Write Disable
+ Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
+ Disable bit. For security recommendations, SPD write disable bit must be set.
+ $EN_DIS
+**/
+ UINT8 SmbusSpdWriteDisable;
+
+/** Offset 0x067A - Enable/Disable SA OcSupport
+ Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
+ $EN_DIS
+**/
+ UINT8 SaOcSupport;
+
+/** Offset 0x067B - Reserved
+**/
+ UINT8 Reserved58[18];
+
+/** Offset 0x068D - Over clocking support
+ Over clocking support; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 OcSupport;
+
+/** Offset 0x068E - Reserved
+**/
+ UINT8 Reserved59;
+
+/** Offset 0x068F - Realtime Memory Timing
+ 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
+ realtime memory timing changes after MRC_DONE.
+ 0: Disabled, 1: Enabled
+**/
+ UINT8 RealtimeMemoryTiming;
+
+/** Offset 0x0690 - core voltage override
+ The core voltage override which is applied to the entire range of cpu core frequencies.
+ Valid Range 0 to 2000
+**/
+ UINT16 CoreVoltageOverride;
+
+/** Offset 0x0692 - Core Turbo voltage Offset
+ The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
+**/
+ UINT16 CoreVoltageOffset;
+
+/** Offset 0x0694 - Core PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
+**/
+ UINT8 CorePllVoltageOffset;
+
+/** Offset 0x0695 - AVX2 Ratio Offset
+ 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
+ vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
+**/
+ UINT8 Avx2RatioOffset;
+
+/** Offset 0x0696 - BCLK Adaptive Voltage Enable
+ When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
+ Disable;<b> 1: Enable
+ $EN_DIS
+**/
+ UINT8 BclkAdaptiveVoltage;
+
+/** Offset 0x0697 - Ring Downbin
+ Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
+ lower than the core ratio.0: Disable; <b>1: Enable.</b>
+ $EN_DIS
+**/
+ UINT8 RingDownBin;
+
+/** Offset 0x0698 - Row Hammer pTRR LFSR0 Mask
+ Row Hammer pTRR LFSR0 Mask, 1/2^(value)
+**/
+ UINT8 Lfsr0Mask;
+
+/** Offset 0x0699 - Margin Limit Check
+ Margin Limit Check. Choose level of margin check
+ 0:Disable, 1:L1, 2:L2, 3:Both
+**/
+ UINT8 MarginLimitCheck;
+
+/** Offset 0x069A - Row Hammer pTRR LFSR1 Mask
+ Row Hammer pTRR LFSR1 Mask, 1/2^(value)
+**/
+ UINT8 Lfsr1Mask;
+
+/** Offset 0x069B - Reserved
+**/
+ UINT8 Reserved60[2];
+
+/** Offset 0x069D - TjMax Offset
+ TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
+ TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
+**/
+ UINT8 TjMaxOffset;
+
+/** Offset 0x069E - Reserved
+**/
+ UINT8 Reserved61[48];
+
+/** Offset 0x06CE - Core VF Point Offset
+ Array used to specifies the Core Voltage Offset applied to the each selected VF
+ Point. This voltage is specified in millivolts.
+**/
+ UINT16 CoreVfPointOffset[15];
+
+/** Offset 0x06EC - Core VF Point Offset Prefix
+ Sets the CoreVfPointOffset value as positive or negative for corresponding core
+ VF Point; <b>0: Positive </b>; 1: Negative.
+ 0:Positive, 1:Negative
+**/
+ UINT8 CoreVfPointOffsetPrefix[15];
+
+/** Offset 0x06FB - Core VF Point Ratio
+ Array for the each selected Core VF Point to display the ration.
+**/
+ UINT8 CoreVfPointRatio[15];
+
+/** Offset 0x070A - Reserved
+**/
+ UINT8 Reserved62[26];
+
+/** Offset 0x0724 - Per Core Max Ratio override
+ Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
+ favored core ratio to each Core. <b>0: Disable</b>, 1: enable
+ $EN_DIS
+**/
+ UINT8 PerCoreRatioOverride;
+
+/** Offset 0x0725 - Reserved
+**/
+ UINT8 Reserved63[25];
+
+/** Offset 0x073E - Per Core Current Max Ratio
+ Array for the Per Core Max Ratio
+**/
+ UINT8 PerCoreRatio[8];
+
+/** Offset 0x0746 - Reserved
+**/
+ UINT8 Reserved64[8];
+
+/** Offset 0x074E - Pvd Ratio Threshold for SOC/CPU die
+ Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
+ (P0 to Pn) to select the multiplier so that the output is within the DCO frequency
+ range. As per the die selected, this threshold is applied to SA and MC/CMI PLL
+ for SOC die and SA, Ring and Atom PLL for CPU die. Range 0-63. When the threshold
+ is 0, static PVD ratio is selected based on the PVD Mode for SOC. <b>0: Default</b>.
+**/
+ UINT8 PvdRatioThreshold;
+
+/** Offset 0x074F - Reserved
+**/
+ UINT8 Reserved65[65];
+
+/** Offset 0x0790 - CPU BCLK OC Frequency
+ CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
+ 40Mhz-1000Mhz.
+**/
+ UINT32 CpuBclkOcFrequency;
+
+/** Offset 0x0794 - Reserved
+**/
+ UINT8 Reserved66[13];
+
+/** Offset 0x07A1 - Avx2 Voltage Guardband Scaling Factor
+ AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
+ 1/100 units, where a value of 125 would apply a 1.25 scale factor.
+**/
+ UINT8 Avx2VoltageScaleFactor;
+
+/** Offset 0x07A2 - Ring PLL voltage offset
+ Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
+**/
+ UINT8 RingPllVoltageOffset;
+
+/** Offset 0x07A3 - Reserved
+**/
+ UINT8 Reserved67[5];
+
+/** Offset 0x07A8 - Enable PCH ISH Controller
+ 0: Disable, 1: Enable (Default) ISH Controller
+ $EN_DIS
+**/
+ UINT8 PchIshEnable;
+
+/** Offset 0x07A9 - Reserved
+**/
+ UINT8 Reserved68;
+
+/** Offset 0x07AA - BiosSize
+ The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
+ 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
+ Range) so that a BIOS Update Script can be stored in the DPR.
+**/
+ UINT16 BiosSize;
+
+/** Offset 0x07AC - BiosGuard
+ Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
+ $EN_DIS
+**/
+ UINT8 BiosGuard;
+
+/** Offset 0x07AD
+**/
+ UINT8 BiosGuardToolsInterface;
+
+/** Offset 0x07AE - Txt
+ Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
+ Execution Technology. Changes require a full power cycle to take effect. <b>0:
+ Disable</b>, 1: Enable
+ $EN_DIS
+**/
+ UINT8 Txt;
+
+/** Offset 0x07AF - Skip Stop PBET Timer Enable/Disable
+ Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 SkipStopPbet;
+
+/** Offset 0x07B0 - Reserved
+**/
+ UINT8 Reserved69[38];
+
+/** Offset 0x07D6 - BIST on Reset
+ Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 BistOnReset;
+
+/** Offset 0x07D7 - Enable or Disable VMX
+ Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
+ provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 VmxEnable;
+
+/** Offset 0x07D8 - Processor Early Power On Configuration FCLK setting
+ FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>.
+ <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved
+ 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
+**/
+ UINT8 FClkFrequency;
+
+/** Offset 0x07D9 - Enable CPU CrashLog
+ Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 CpuCrashLogEnable;
+
+/** Offset 0x07DA - Enable or Disable TME
+ Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks.
+ <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TmeEnable;
+
+/** Offset 0x07DB - CPU Run Control
+ Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
+ No Change</b>
+ 0:Disabled, 1:Enabled, 2:No Change
+**/
+ UINT8 DebugInterfaceEnable;
+
+/** Offset 0x07DC - CPU Run Control Lock
+ Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 DebugInterfaceLockEnable;
+
+/** Offset 0x07DD - Enable CPU CrashLog GPRs dump
+ Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
+ disable Smm GPRs dump
+ 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
+**/
+ UINT8 CrashLogGprs;
+
+/** Offset 0x07DE - Over clocking Lock
+ Lock Overclocking. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 OcLock;
+
+/** Offset 0x07DF - CPU ratio value
+ This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio
+ set by Hardware (HFM). Valid Range 0 to 63.
+**/
+ UINT8 CpuRatio;
+
+/** Offset 0x07E0 - Number of active big cores
+ Number of P-cores to enable in each processor package. Note: Number of P-Cores and
+ E-Cores are looked at together. When both are {0,0
+ 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores
+**/
+ UINT8 ActiveCoreCount;
+
+/** Offset 0x07E1 - Reserved
+**/
+ UINT8 Reserved70[3];
+
+/** Offset 0x07E4 - PrmrrSize
+ Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
+**/
+ UINT32 PrmrrSize;
+
+/** Offset 0x07E8 - Tseg Size
+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+ 0x0400000:4MB, 0x01000000:16MB
+**/
+ UINT32 TsegSize;
+
+/** Offset 0x07EC - SmmRelocationEnable Enable
+ Enable or Disable SmmRelocationEnable. <b>0: Disable</b>, 1:Enable
+ $EN_DIS
+**/
+ UINT8 SmmRelocationEnable;
+
+/** Offset 0x07ED - TCC Activation Offset
+ TCC Activation Offset. Offset from factory set TCC activation temperature at which
+ the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
+ Temperature, in volts. <b>Default = 0h</b>.
+**/
+ UINT8 TccActivationOffset;
+
+/** Offset 0x07EE - Reserved
+**/
+ UINT8 Reserved71[90];
+
+/** Offset 0x0848 - SinitMemorySize
+ Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
+**/
+ UINT32 SinitMemorySize;
+
+/** Offset 0x084C - Reserved
+**/
+ UINT8 Reserved72[4];
+
+/** Offset 0x0850 - TxtDprMemoryBase
+ Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
+**/
+ UINT64 TxtDprMemoryBase;
+
+/** Offset 0x0858 - TxtHeapMemorySize
+ Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
+**/
+ UINT32 TxtHeapMemorySize;
+
+/** Offset 0x085C - TxtDprMemorySize
+ Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize
+ , 1: enable
+**/
+ UINT32 TxtDprMemorySize;
+
+/** Offset 0x0860 - TxtLcpPdBase
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
+**/
+ UINT64 TxtLcpPdBase;
+
+/** Offset 0x0868 - TxtLcpPdSize
+ Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
+**/
+ UINT64 TxtLcpPdSize;
+
+/** Offset 0x0870 - BiosAcmBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT64 BiosAcmBase;
+
+/** Offset 0x0878 - BiosAcmSize
+ Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
+**/
+ UINT32 BiosAcmSize;
+
+/** Offset 0x087C - ApStartupBase
+ Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
+**/
+ UINT32 ApStartupBase;
+
+/** Offset 0x0880 - TgaSize
+ Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
+**/
+ UINT32 TgaSize;
+
+/** Offset 0x0884 - IsTPMPresence
+ IsTPMPresence default values
+**/
+ UINT8 IsTPMPresence;
+
+/** Offset 0x0885 - Reserved
+**/
+ UINT8 Reserved73[157];
+
+/** Offset 0x0922 - Thermal Design Current enable/disable
+ Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
+ [1] for GT, [2] for SA, [3] through [5] are Reserved.
+**/
+ UINT8 TdcEnable[6];
+
+/** Offset 0x0928 - Reserved
+**/
+ UINT8 Reserved74[24];
+
+/** Offset 0x0940 - Thermal Design Current time window
+ PSYS Offset defined in 1/1000 increments. <b>0 - Auto</b> This is an 32-bit signed
+ value (2's complement). Units 1/1000, Range is [-128000, 127999]. For an offset
+ of 25.348, enter 25348.
+**/
+ UINT8 TdcTimeWindow[24];
+
+/** Offset 0x0958 - Reserved
+**/
+ UINT8 Reserved75[8];
+
+/** Offset 0x0960 - DLVR RFI Enable
+ Enable/Disable DLVR RFI frequency hopping. 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 DlvrRfiEnable;
+
+/** Offset 0x0961 - Reserved
+**/
+ UINT8 Reserved76[25];
+
+/** Offset 0x097A - Enable/Disable VR FastVmode. The VR will initiate reactive protection if Fast Vmode is enabled.
+ Enable/Disable VR FastVmode; <b>0: Disable</b>; 1: Enable.For all VR by domain
+ 0: Disable, 1: Enable
+**/
+ UINT8 EnableFastVmode[6];
+
+/** Offset 0x0980 - Reserved
+**/
+ UINT8 Reserved77[26];
+
+/** Offset 0x099A - PCH Port80 Route
+ Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
+ $EN_DIS
+**/
+ UINT8 PchPort80Route;
+
+/** Offset 0x099B - GPIO Override
+ Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
+ before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
+ configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use
+**/
+ UINT8 GpioOverride;
+
+/** Offset 0x099C - Reserved
+**/
+ UINT8 Reserved78[4];
+
+/** Offset 0x09A0 - PMR Size
+ Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
+**/
+ UINT32 DmaBufferSize;
+
+/** Offset 0x09A4 - The policy for VTd driver behavior
+ BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
+**/
+ UINT8 PreBootDmaMask;
+
+/** Offset 0x09A5 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table
+ 0=Disable/Clear, 1=Enable/Set
+ $EN_DIS
+**/
+ UINT8 DmaControlGuarantee;
+
+/** Offset 0x09A6 - Disable VT-d
+ 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
+ $EN_DIS
+**/
+ UINT8 VtdDisable;
+
+/** Offset 0x09A7 - Reserved
+**/
+ UINT8 Reserved79;
+
+/** Offset 0x09A8 - Base addresses for VT-d function MMIO access
+ Base addresses for VT-d MMIO access per VT-d engine
+**/
+ UINT32 VtdBaseAddress[9];
+
+/** Offset 0x09CC - Reserved
+**/
+ UINT8 Reserved80[20];
+
+/** Offset 0x09E0 - MMIO Size
+ Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB
+**/
+ UINT16 MmioSize;
+
+/** Offset 0x09E2 - MMIO size adjustment for AUTO mode
+ Positive number means increasing MMIO size, Negative value means decreasing MMIO
+ size: 0 (Default)=no change to AUTO mode MMIO size
+**/
+ UINT16 MmioSizeAdjustment;
+
+/** Offset 0x09E4 - Reserved
+**/
+ UINT8 Reserved81[36];
+
+/** Offset 0x0A08 - Enable above 4GB MMIO resource support
+ Enable/disable above 4GB MMIO resource support
+ $EN_DIS
+**/
+ UINT8 EnableAbove4GBMmio;
+
+/** Offset 0x0A09 - Enable/Disable SA CRID
+ Enable: SA CRID, Disable (Default): SA CRID
+ $EN_DIS
+**/
+ UINT8 CridEnable;
+
+/** Offset 0x0A0A - Reserved
+**/
+ UINT8 Reserved82[34];
+
+/** Offset 0x0A2C - Enable/Disable CrashLog Device
+ Enable or Disable CrashLog/Telemetry Device 0- Disable, <b>1- Enable</b>
+ $EN_DIS
+**/
+ UINT32 CpuCrashLogDevice;
+
+/** Offset 0x0A30 - Reserved
+**/
+ UINT8 Reserved83[17];
+
+/** Offset 0x0A41 - Platform Debug Option
+ Enabled Trace active: TraceHub is enabled and trace is active, blocks s0ix.\n
+ \n
+ Enabled Trace ready: TraceHub is enabled and allowed S0ix.\n
+ \n
+ Enabled Trace power off: TraceHub is powergated, provide setting close to functional
+ low power state\n
+ \n
+ Manual: user needs to configure Advanced Debug Settings manually, aimed at advanced users
+ 0:Disabled, 2:Enabled Trace Active, 4:Enabled Trace Ready, 6:Enable Trace Power-Off, 7:Manual
+**/
+ UINT8 PlatformDebugOption;
+
+/** Offset 0x0A42 - Reserved
+**/
+ UINT8 Reserved84[14];
+
+/** Offset 0x0A50 - Program GPIOs for LFP on DDI port-A device
+ 0=Disabled,1(Default)=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortAConfig;
+
+/** Offset 0x0A51 - Reserved
+**/
+ UINT8 Reserved85[3];
+
+/** Offset 0x0A54 - Program GPIOs for LFP on DDI port-B device
+ 0(Default)=Disabled,1=eDP, 2=MIPI DSI
+ 0:Disabled, 1:eDP, 2:MIPI DSI
+**/
+ UINT8 DdiPortBConfig;
+
+/** Offset 0x0A55 - Enable or disable HPD of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortAHpd;
+
+/** Offset 0x0A56 - Enable or disable HPD of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBHpd;
+
+/** Offset 0x0A57 - Enable or disable HPD of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCHpd;
+
+/** Offset 0x0A58 - Enable or disable HPD of DDI port 1
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Hpd;
+
+/** Offset 0x0A59 - Enable or disable HPD of DDI port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Hpd;
+
+/** Offset 0x0A5A - Enable or disable HPD of DDI port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Hpd;
+
+/** Offset 0x0A5B - Enable or disable HPD of DDI port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Hpd;
+
+/** Offset 0x0A5C - Enable or disable DDC of DDI port A
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortADdc;
+
+/** Offset 0x0A5D - Enable or disable DDC of DDI port B
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortBDdc;
+
+/** Offset 0x0A5E - Enable or disable DDC of DDI port C
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPortCDdc;
+
+/** Offset 0x0A5F - Enable DDC setting of DDI Port 1
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort1Ddc;
+
+/** Offset 0x0A60 - Enable DDC setting of DDI Port 2
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort2Ddc;
+
+/** Offset 0x0A61 - Enable DDC setting of DDI Port 3
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort3Ddc;
+
+/** Offset 0x0A62 - Enable DDC setting of DDI Port 4
+ 0(Default)=Disable, 1=Enable
+ $EN_DIS
+**/
+ UINT8 DdiPort4Ddc;
+
+/** Offset 0x0A63 - Reserved
+**/
+ UINT8 Reserved86[5];
+
+/** Offset 0x0A68 - Temporary MMIO address for GMADR
+ The reference code will use this as Temporary MMIO address space to access GMADR
+ Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to
+ (GmAdr + 256MB). Default is (PciExpressBaseAddress - 256MB) to (PciExpressBaseAddress - 0x1)
+**/
+ UINT64 LMemBar;
+
+/** Offset 0x0A70 - Temporary MMIO address for GTTMMADR
+ The reference code will use this as Temporary MMIO address space to access GTTMMADR
+ Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
+ to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
+ + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB)
+**/
+ UINT64 GttMmAdr;
+
+/** Offset 0x0A78 - Reserved
+**/
+ UINT8 Reserved87[2];
+
+/** Offset 0x0A7A - Enable/Disable Memory Bandwidth Compression
+ 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 MemoryBandwidthCompression;
+
+/** Offset 0x0A7B - Panel Power Enable
+ Control for enabling/disabling VDD force bit (Required only for early enabling of
+ eDP panel). 0=Disable, 1(Default)=Enable
+ $EN_DIS
+**/
+ UINT8 PanelPowerEnable;
+
+/** Offset 0x0A7C - Selection of the primary display device
+ 3(Default)=AUTO, 0=IGFX, 4=Hybrid Graphics
+ 3:AUTO, 0:IGFX, 4:HG
+**/
+ UINT8 PrimaryDisplay;
+
+/** Offset 0x0A7D - TCSS USB HOST (xHCI) Enable
+ Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
+ $EN_DIS
+**/
+ UINT8 TcssXhciEn;
+
+/** Offset 0x0A7E - Reserved
+**/
+ UINT8 Reserved88[4];
+
+/** Offset 0x0A82 - TCSS Type C Port 0
+ Set TCSS Type C Port 0 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
+ 7=FULL_FUN
+ 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
+**/
+ UINT8 TcssPort0;
+
+/** Offset 0x0A83 - TCSS Type C Port 1
+ Set TCSS Type C Port 1 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
+ 7=FULL_FUN
+ 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
+**/
+ UINT8 TcssPort1;
+
+/** Offset 0x0A84 - TCSS Type C Port 2
+ Set TCSS Type C Port 2 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
+ 7=FULL_FUN
+ 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
+**/
+ UINT8 TcssPort2;
+
+/** Offset 0x0A85 - TCSS Type C Port 3
+ Set TCSS Type C Port 3 Type, Options are 0=DISABLE, 1=DP_ONLY, 2=NO_TBT, 3=NO_PCIE,
+ 7=FULL_FUN
+ 0:DISABLE, 1:DP_ONLY, 2:NO_TBT, 3: NO_PCIE, 7:FULL_FUN
+**/
+ UINT8 TcssPort3;
+
+/** Offset 0x0A86 - Reserved
+**/
+ UINT8 Reserved89[2];
+
+/** Offset 0x0A88 - TypeC port GPIO setting
+ GPIO Pin number for Type C Aux orientation setting, use the GpioPad that is defined
+ in GpioPinsXXX.h as argument.(XXX is platform name, Ex: Ptl = PantherLake)
+**/
+ UINT32 IomTypeCPortPadCfg[12];
+
+/** Offset 0x0AB8 - TCSS Aux Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssAuxOri;
+
+/** Offset 0x0ABA - TCSS HSL Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssHslOri;
+
+/** Offset 0x0ABC - CNVi DDR RFI Mitigation
+ Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviDdrRfim;
+
+/** Offset 0x0ABD - SOC Trace Hub Mode
+ Enable/Disable SOC TraceHub
+ $EN_DIS
+**/
+ UINT8 SocTraceHubMode;
+
+/** Offset 0x0ABE - Reserved
+**/
+ UINT8 Reserved90[4];
+
+/** Offset 0x0AC2 - Internal Graphics Pre-allocated Memory
+ Size of memory preallocated for internal graphics.
+ 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0xF0:4MB, 0xF1:8MB, 0xF2:12MB,
+ 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB,
+ 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
+**/
+ UINT16 IgdDvmt50PreAlloc;
+
+/** Offset 0x0AC4 - Internal Graphics
+ Enable/disable internal graphics.
+ $EN_DIS
+**/
+ UINT8 InternalGraphics;
+
+/** Offset 0x0AC5 - Reserved
+**/
+ UINT8 Reserved91[7];
+
+/** Offset 0x0ACC - Fore Single Rank config
+ Enables/Disable Fore Single Rank config
+ $EN_DIS
+**/
+ UINT32 DynamicMemoryBoost;
+
+/** Offset 0x0AD0 - Fore Single Rank config
+ Enables/Disable Fore Single Rank config
+ $EN_DIS
+**/
+ UINT32 RealtimeMemoryFrequency;
+
+/** Offset 0x0AD4 - Reserved
+**/
+ UINT8 Reserved92[9];
+
+/** Offset 0x0ADD - Vref Offset
+ Offset to be applied to DDRDATACH0_CR_DDRCRDATAOFFSETTRAIN.VrefOffset
+ 0xFA:-6, 0xFB:-5, 0xFC:-4, 0xFD:-3, 0xFE:-2, 0xFF:-1, 0:0, 1:+1, 2:+2, 3:+3, 4:+4,
+ 5:+5, 6:+6
+**/
+ UINT8 VrefOffset;
+
+/** Offset 0x0ADE - Reserved
+**/
+ UINT8 Reserved93[2];
+
+/** Offset 0x0AE0 - tRRSG Delta
+ Delay between Read-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
+ delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+ of [-127..127]
+**/
+ UINT8 tRRSG;
+
+/** Offset 0x0AE1 - tRRDG Delta
+ Delay between Read-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
+ delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+ of [-127..127]
+**/
+ UINT8 tRRDG;
+
+/** Offset 0x0AE2 - tRRDR Delta
+ Delay between Read-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
+ is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+ [-127..127]
+**/
+ UINT8 tRRDR;
+
+/** Offset 0x0AE3 - tRRDD Delta
+ Delay between Read-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
+ is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+ [-127..127]
+**/
+ UINT8 tRRDD;
+
+/** Offset 0x0AE4 - tWRSG Delta
+ Delay between Write-to-Read commands in the same Bank Group. 0 - Auto. Signed TAT
+ delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+ of [-127..127]
+**/
+ UINT8 tWRSG;
+
+/** Offset 0x0AE5 - tWRDG Delta
+ Delay between Write-to-Read commands in different Bank Group. 0 - Auto. Signed TAT
+ delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+ of [-127..127]
+**/
+ UINT8 tWRDG;
+
+/** Offset 0x0AE6 - tWRDR Delta
+ Delay between Write-to-Read commands in different Ranks. 0 - Auto. Signed TAT delta
+ is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+ [-127..127]
+**/
+ UINT8 tWRDR;
+
+/** Offset 0x0AE7 - tWRDD Delta
+ Delay between Write-to-Read commands in different DIMMs. 0 - Auto. Signed TAT delta
+ is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+ [-127..127]
+**/
+ UINT8 tWRDD;
+
+/** Offset 0x0AE8 - tWWSG Delta
+ Delay between Write-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
+ delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+ of [-127..127]
+**/
+ UINT8 tWWSG;
+
+/** Offset 0x0AE9 - tWWDG Delta
+ Delay between Write-to-Write commands in different Bank Group. 0 - Auto. Signed
+ TAT delta is (Value - 128). Input value range of [1..255] will give a TAT delta
+ range of [-127..127]
+**/
+ UINT8 tWWDG;
+
+/** Offset 0x0AEA - tWWDR Delta
+ Delay between Write-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
+ is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+ [-127..127]
+**/
+ UINT8 tWWDR;
+
+/** Offset 0x0AEB - tWWDD Delta
+ Delay between Write-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
+ is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+ [-127..127]
+**/
+ UINT8 tWWDD;
+
+/** Offset 0x0AEC - tRWSG Delta
+ Delay between Read-to-Write commands in the same Bank Group. 0 - Auto. Signed TAT
+ delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+ of [-127..127]
+**/
+ UINT8 tRWSG;
+
+/** Offset 0x0AED - tRWDG Delta
+ Delay between Read-to-Write commands in different Bank Group. 0 - Auto. Signed TAT
+ delta is (Value - 128). Input value range of [1..255] will give a TAT delta range
+ of [-127..127]
+**/
+ UINT8 tRWDG;
+
+/** Offset 0x0AEE - tRWDR Delta
+ Delay between Read-to-Write commands in different Ranks. 0 - Auto. Signed TAT delta
+ is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+ [-127..127]
+**/
+ UINT8 tRWDR;
+
+/** Offset 0x0AEF - tRWDD Delta
+ Delay between Read-to-Write commands in different DIMMs. 0 - Auto. Signed TAT delta
+ is (Value - 128). Input value range of [1..255] will give a TAT delta range of
+ [-127..127]
+**/
+ UINT8 tRWDD;
+
+/** Offset 0x0AF0 - Reserved
+**/
+ UINT8 Reserved94[13];
+
+/** Offset 0x0AFD - Fake SAGV
+ Fake SAGV: 0:Disabled, 1:Enabled
+ $EN_DIS
+**/
+ UINT8 PprForceRepair;
+
+/** Offset 0x0AFE - Fake SAGV
+ Fake SAGV: 0:Disabled, 1:Enabled
+ $EN_DIS
+**/
+ UINT8 PprRepairBank;
+
+/** Offset 0x0AFF - Reserved
+**/
+ UINT8 Reserved95[25];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -62,11 +2915,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0060
+/** Offset 0x0B18
**/
- UINT8 UnusedUpdSpace4[6];
+ UINT8 UnusedUpdSpace54[6];
-/** Offset 0x0066
+/** Offset 0x0B1E
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
index 938c283be3..6e1a316ece 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/FspsUpd.h
@@ -39,6 +39,26 @@ are permitted provided that the following conditions are met:
///
+/// Azalia Header structure
+///
+typedef struct {
+ UINT16 VendorId; ///< Codec Vendor ID
+ UINT16 DeviceId; ///< Codec Device ID
+ UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
+ UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
+ UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
+ UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
+} AZALIA_HEADER;
+
+///
+/// Audio Azalia Verb Table structure
+///
+typedef struct {
+ AZALIA_HEADER Header; ///< AZALIA PCH header
+ UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
+} AUDIO_AZALIA_VERB_TABLE;
+
+///
/// Refer to the definition of PCH_INT_PIN
///
typedef enum {
@@ -58,10 +78,2225 @@ typedef struct {
UINT8 Irq; ///< IRQ to be set for device.
} SI_PCH_DEVICE_INTERRUPT_CONFIG;
-/** FSP S Configuration
+#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
+
+
+/** Fsp S Configuration
**/
typedef struct {
- /* Placeholder for FSP_S_CONFIG UPDs */
+
+/** Offset 0x0040 - BgpdtHash[6]
+ BgpdtHash values
+**/
+ UINT64 BgpdtHash[6];
+
+/** Offset 0x0070 - BiosGuardAttr
+ BiosGuardAttr default values
+**/
+ UINT32 BiosGuardAttr;
+
+/** Offset 0x0074 - Reserved
+**/
+ UINT8 Reserved0[4];
+
+/** Offset 0x0078 - BiosGuardModulePtr
+ BiosGuardModulePtr default values
+**/
+ UINT64 BiosGuardModulePtr;
+
+/** Offset 0x0080 - Reserved
+**/
+ UINT8 Reserved1[17];
+
+/** Offset 0x0091 - PCH eSPI Link Configuration Lock (SBLCL)
+ Enable/Disable lock of communication through SET_CONFIG/GET_CONFIG to eSPI target
+ addresseses from range 0x0 - 0x7FF
+ $EN_DIS
+**/
+ UINT8 PchEspiLockLinkConfiguration;
+
+/** Offset 0x0092 - Enable Host C10 reporting through eSPI
+ Enable/disable Host C10 reporting to Device via eSPI Virtual Wire.
+ $EN_DIS
+**/
+ UINT8 PchEspiHostC10ReportEnable;
+
+/** Offset 0x0093 - Espi Lgmr Memory Range decode
+ This option enables or disables espi lgmr
+ $EN_DIS
+**/
+ UINT8 PchEspiLgmrEnable;
+
+/** Offset 0x0094 - Reserved
+**/
+ UINT8 Reserved2[4];
+
+/** Offset 0x0098 - CpuBistData
+ Pointer CPU BIST Data
+**/
+ UINT64 CpuBistData;
+
+/** Offset 0x00A0 - CpuMpPpi
+ <b>Optional</b> pointer to the boot loader's implementation of EFI_PEI_MP_SERVICES_PPI.
+ If not NULL, FSP will use the boot loader's implementation of multiprocessing.
+ See section 5.1.4 of the FSP Integration Guide for more details.
+**/
+ UINT64 CpuMpPpi;
+
+/** Offset 0x00A8 - Enable/Disable CrashLog
+ Enable(Default): Enable CPU CrashLog, Disable: Disable CPU CrashLog
+ $EN_DIS
+**/
+ UINT8 CpuCrashLogEnable;
+
+/** Offset 0x00A9 - Reserved
+**/
+ UINT8 Reserved3[7];
+
+/** Offset 0x00B0 - MicrocodeRegionBase
+ Memory Base of Microcode Updates
+**/
+ UINT64 MicrocodeRegionBase;
+
+/** Offset 0x00B8 - MicrocodeRegionSize
+ Size of Microcode Updates
+**/
+ UINT64 MicrocodeRegionSize;
+
+/** Offset 0x00C0 - Enable or Disable TXT
+ Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
+ Execution Technology. Changes require a full power cycle to take effect. <b>0:
+ Disable</b>, 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TxtEnable;
+
+/** Offset 0x00C1 - PpinSupport to view Protected Processor Inventory Number
+ PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn
+ off this feature. When 'PPIN Enable Mode' is selected, this shows second option
+ where feature can be enabled based on EOM (End of Manufacturing) flag or it is
+ always enabled
+ 0: Disable, 1: Enable, 2: Auto
+**/
+ UINT8 PpinSupport;
+
+/** Offset 0x00C2 - Advanced Encryption Standard (AES) feature
+ Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
+ $EN_DIS
+**/
+ UINT8 AesEnable;
+
+/** Offset 0x00C3 - AvxDisable
+ Enable/Disable the AVX and AVX2 Instructions
+ 0: Enable, 1: Disable
+**/
+ UINT8 AvxDisable;
+
+/** Offset 0x00C4 - Reserved
+**/
+ UINT8 Reserved4;
+
+/** Offset 0x00C5 - P-state ratios for max 16 version of custom P-state table
+ P-state ratios for max 16 version of custom P-state table. This table is used for
+ OS versions limited to a max of 16 P-States. If the first entry of this table is
+ 0, or if Number of Entries is 16 or less, then this table will be ignored, and
+ up to the top 16 values of the StateRatio table will be used instead. Valid Range
+ of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatioMax16[16];
+
+/** Offset 0x00D5 - Enable or Disable Intel SpeedStep Technology
+ Allows more than two frequency ranges to be supported. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 Eist;
+
+/** Offset 0x00D6 - Enable or Disable Energy Efficient P-state
+ Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access
+ to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support
+ for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS
+ MSR and CPUID Function will read 1 indicating Energy Efficient policy setting is
+ supported. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientPState;
+
+/** Offset 0x00D7 - Enable or Disable Energy Efficient Turbo
+ Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically
+ lower the turbo frequency to increase efficiency. Recommended only to disable in
+ overclocking situations where turbo frequency must remain constant. Otherwise,
+ leave enabled. <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 EnergyEfficientTurbo;
+
+/** Offset 0x00D8 - Enable or Disable T states
+ Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 TStates;
+
+/** Offset 0x00D9 - Enable or Disable Thermal Reporting
+ Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 EnableAllThermalFunctions;
+
+/** Offset 0x00DA - Enable or Disable CPU power states (C-states)
+ Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not
+ 100% utilized. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 Cx;
+
+/** Offset 0x00DB - Configure C-State Configuration Lock
+ Configure MSR to CFG Lock bit. 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 PmgCstCfgCtrlLock;
+
+/** Offset 0x00DC - Enable or Disable Enhanced C-states
+ Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores
+ enter C-State. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C1e;
+
+/** Offset 0x00DD - Enable or Disable Package Cstate Demotion
+ Enable or Disable Package C-State Demotion. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 PkgCStateDemotion;
+
+/** Offset 0x00DE - Enable or Disable Package Cstate UnDemotion
+ Enable or Disable Package C-State Un-Demotion. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 PkgCStateUnDemotion;
+
+/** Offset 0x00DF - Enable or Disable CState-Pre wake
+ Disable - to disable the Cstate Pre-Wake. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 CStatePreWake;
+
+/** Offset 0x00E0 - Enable or Disable TimedMwait Support.
+ Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
+ $EN_DIS
+**/
+ UINT8 TimedMwait;
+
+/** Offset 0x00E1 - Set the Max Pkg Cstate
+ Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value.
+ Auto: Initializes to deepest available Package C State Limit. Valid values 0 -
+ C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 -
+ CPU Default, <b>255 - Auto</b>
+**/
+ UINT8 PkgCStateLimit;
+
+/** Offset 0x00E2 - Reserved
+**/
+ UINT8 Reserved5[2];
+
+/** Offset 0x00E4 - Interrupt Redirection Mode Select
+ Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1:
+ Round robin; 2: Hash vector; 7: No change.
+**/
+ UINT8 PpmIrmSetting;
+
+/** Offset 0x00E5 - Turbo Mode
+ Enable/Disable processor Turbo Mode. 0:disable, <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 TurboMode;
+
+/** Offset 0x00E6 - Reserved
+**/
+ UINT8 Reserved6;
+
+/** Offset 0x00E7 - P-state ratios for custom P-state table
+ P-state ratios for custom P-state table. NumberOfEntries has valid range between
+ 0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
+ are configurable. Valid Range of each entry is 0 to 0x7F
+**/
+ UINT8 StateRatio[40];
+
+/** Offset 0x010F - Custom Ratio State Entries
+ The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
+ ratio table. Sets the number of custom P-states. At least 2 states must be present
+**/
+ UINT8 NumberOfEntries;
+
+/** Offset 0x0110 - Max P-State Ratio
+ Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F
+**/
+ UINT8 MaxRatio;
+
+/** Offset 0x0111 - Reserved
+**/
+ UINT8 Reserved7;
+
+/** Offset 0x0112 - Turbo settings Lock
+ Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT
+ MSR will be locked and a reset will be required to unlock the register. <b>0: Disable;
+ </b> 1: Enable
+ $EN_DIS
+**/
+ UINT8 TurboPowerLimitLock;
+
+/** Offset 0x0113 - Reserved
+**/
+ UINT8 Reserved8[33];
+
+/** Offset 0x0134 - Race To Halt
+ Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
+ in order to enter pkg C-State faster to reduce overall power. 0: Disable; <b>1:
+ Enable</b>
+ $EN_DIS
+**/
+ UINT8 RaceToHalt;
+
+/** Offset 0x0135 - Enable or Disable C1 Cstate Demotion
+ Enable or Disable C1 Cstate Auto Demotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C1StateAutoDemotion;
+
+/** Offset 0x0136 - Enable or Disable C1 Cstate UnDemotion
+ Enable or Disable C1 Cstate Un-Demotion. Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 C1StateUnDemotion;
+
+/** Offset 0x0137 - Minimum Ring ratio limit override
+ Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MinRingRatioLimit;
+
+/** Offset 0x0138 - Maximum Ring ratio limit override
+ Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
+ ratio limit
+**/
+ UINT8 MaxRingRatioLimit;
+
+/** Offset 0x0139 - Reserved
+**/
+ UINT8 Reserved9;
+
+/** Offset 0x013A - Enable or Disable HWP
+ Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
+ CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; <b>1:
+ Enable;</b>
+ $EN_DIS
+**/
+ UINT8 Hwp;
+
+/** Offset 0x013B - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+ Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 HwpInterruptControl;
+
+/** Offset 0x013C - Enable or Disable HwP Autonomous Per Core P State OS control
+ Disable Autonomous PCPS Autonomous will request the same value for all cores all
+ the time. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnableHwpAutoPerCorePstate;
+
+/** Offset 0x013D - Enable or Disable HwP Autonomous EPP Grouping
+ Enable EPP grouping Autonomous will request the same values for all cores with same
+ EPP. Disable EPP grouping autonomous will not necessarily request same values for
+ all cores with same EPP. 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 EnableHwpAutoEppGrouping;
+
+/** Offset 0x013E - Reserved
+**/
+ UINT8 Reserved10[4];
+
+/** Offset 0x0142 - Enable or Disable MLC Streamer Prefetcher
+ Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 MlcStreamerPrefetcher;
+
+/** Offset 0x0143 - Enable or Disable MLC Spatial Prefetcher
+ Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
+ $EN_DIS
+**/
+ UINT8 MlcSpatialPrefetcher;
+
+/** Offset 0x0144 - Enable or Disable Monitor /MWAIT instructions
+ Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner
+ should not set in MWAIT Loop. 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 MonitorMwaitEnable;
+
+/** Offset 0x0145 - Enable or Disable initialization of machine check registers
+ Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
+ $EN_DIS
+**/
+ UINT8 MachineCheckEnable;
+
+/** Offset 0x0146 - Control on Processor Trace output scheme
+ Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
+ 0: Single Range Output, 1: ToPA Output
+**/
+ UINT8 ProcessorTraceOutputScheme;
+
+/** Offset 0x0147 - Enable or Disable Processor Trace feature
+ Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 ProcessorTraceEnable;
+
+/** Offset 0x0148 - Reserved
+**/
+ UINT8 Reserved11[3];
+
+/** Offset 0x014B - UFS enable/disable
+ Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
+ 0 and (0,1) to enable controller 1
+ $EN_DIS
+**/
+ UINT8 UfsEnable[2];
+
+/** Offset 0x014D - Reserved
+**/
+ UINT8 Reserved12[2];
+
+/** Offset 0x014F - Enable/Disable PCIe tunneling for USB4
+ Enable/Disable PCIe tunneling for USB4, default is enable
+ $EN_DIS
+**/
+ UINT8 ITbtPcieTunnelingForUsb4;
+
+/** Offset 0x0150 - Reserved
+**/
+ UINT8 Reserved13[4];
+
+/** Offset 0x0154 - ITBTForcePowerOn Timeout value
+ ITBTForcePowerOn value. Specified increment values in miliseconds. Range is 0-1000.
+ 100 = 100 ms.
+**/
+ UINT16 ITbtForcePowerOnTimeoutInMs;
+
+/** Offset 0x0156 - ITbtConnectTopology Timeout value
+ ITbtConnectTopologyTimeout value. Specified increment values in miliseconds. Range
+ is 0-10000. 100 = 100 ms.
+**/
+ UINT16 ITbtConnectTopologyTimeoutInMs;
+
+/** Offset 0x0158 - ITBT DMA LTR
+ TCSS DMA1, DMA2 LTR value
+**/
+ UINT16 ITbtDmaLtr[2];
+
+/** Offset 0x015C - Reserved
+**/
+ UINT8 Reserved14[12];
+
+/** Offset 0x0168 - IEH Mode
+ Integrated Error Handler Mode, 0: Bypass, 1: Enable
+ 0: Bypass, 1:Enable
+**/
+ UINT8 IehMode;
+
+/** Offset 0x0169 - RTC BIOS Interface Lock
+ Enable RTC BIOS interface lock. When set, prevents RTC TS (BUC.TS) from being changed.
+ $EN_DIS
+**/
+ UINT8 RtcBiosInterfaceLock;
+
+/** Offset 0x016A - RTC Cmos Memory Lock
+ Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
+ and and lower 128-byte bank of RTC RAM.
+ $EN_DIS
+**/
+ UINT8 RtcMemoryLock;
+
+/** Offset 0x016B - AMT Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable AMT functionality.
+ $EN_DIS
+**/
+ UINT8 AmtEnabled;
+
+/** Offset 0x016C - SOL Switch
+ Enable/Disable. 0: Disable, 1: enable, Serial Over Lan enable/disable state by Mebx.
+ Setting is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 AmtSolEnabled;
+
+/** Offset 0x016D - WatchDog Timer Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable WatchDog timer. Setting
+ is invalid if AmtEnabled is 0.
+ $EN_DIS
+**/
+ UINT8 WatchDogEnabled;
+
+/** Offset 0x016E - OS Timer
+ 16 bits Value, Set OS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+ UINT16 WatchDogTimerOs;
+
+/** Offset 0x0170 - BIOS Timer
+ 16 bits Value, Set BIOS watchdog timer. Setting is invalid if AmtEnabled is 0.
+**/
+ UINT16 WatchDogTimerBios;
+
+/** Offset 0x0172 - Iax Switch
+ Enable/Disable. 0: Disable, 1: enable, Enable or disable Iax functionality.
+ $EN_DIS
+**/
+ UINT8 IaxEnable;
+
+/** Offset 0x0173 - Reserved
+**/
+ UINT8 Reserved15;
+
+/** Offset 0x0174 - ISH GP GPIO Pin Muxing
+ Determines ISH GP GPIO Pin muxing. See GPIO_*_MUXING_ISH_GP_x_GPIO_*. 'x' are GP_NUMBER
+**/
+ UINT32 IshGpGpioPinMuxing[12];
+
+/** Offset 0x01A4 - ISH UART Rx Pin Muxing
+ Determines ISH UART Rx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_TXD_*
+**/
+ UINT32 IshUartRxPinMuxing[3];
+
+/** Offset 0x01B0 - ISH UART Tx Pin Muxing
+ Determines ISH UART Tx Pin muxing. See GPIO_*_MUXING_ISH_UARTx_RXD_*
+**/
+ UINT32 IshUartTxPinMuxing[3];
+
+/** Offset 0x01BC - ISH UART Rts Pin Muxing
+ Select ISH UART Rts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_RTS_* for possible values.
+**/
+ UINT32 IshUartRtsPinMuxing[3];
+
+/** Offset 0x01C8 - ISH UART Rts Pin Muxing
+ Select ISH UART Cts Pin muxing. Refer to GPIO_*_MUXING_ISH_UARTx_CTS_* for possible values.
+**/
+ UINT32 IshUartCtsPinMuxing[3];
+
+/** Offset 0x01D4 - ISH I2C SDA Pin Muxing
+ Select ISH I2C SDA Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SDA_* for possible values.
+**/
+ UINT32 IshI2cSdaPinMuxing[3];
+
+/** Offset 0x01E0 - ISH I2C SCL Pin Muxing
+ Select ISH I2C SCL Pin muxing. Refer to GPIO_*_MUXING_ISH_I2Cx_SCL_* for possible values.
+**/
+ UINT32 IshI2cSclPinMuxing[3];
+
+/** Offset 0x01EC - ISH SPI MOSI Pin Muxing
+ Select ISH SPI MOSI Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MOSI_* for possible values.
+**/
+ UINT32 IshSpiMosiPinMuxing[2];
+
+/** Offset 0x01F4 - ISH SPI MISO Pin Muxing
+ Select ISH SPI MISO Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_MISO_* for possible values.
+**/
+ UINT32 IshSpiMisoPinMuxing[2];
+
+/** Offset 0x01FC - ISH SPI CLK Pin Muxing
+ Select ISH SPI CLK Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CLK_* for possible values.
+**/
+ UINT32 IshSpiClkPinMuxing[2];
+
+/** Offset 0x0204 - ISH SPI CS#N Pin Muxing
+ Select ISH SPI CS#N Pin muxing. Refer to GPIO_*_MUXING_ISH_SPIx_CS<N>_* for possible
+ values. N-SPI number, 0-1.
+**/
+ UINT32 IshSpiCsPinMuxing[4];
+
+/** Offset 0x0214 - ISH GP GPIO Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo GP#N GPIO pads termination
+ respectively. #N are GP_NUMBER, not strictly relate to indexes of this table. Index
+ 0-23 -> ISH_GP_0-23, Index 24-25 -> ISH_GP_30-31
+**/
+ UINT8 IshGpGpioPadTermination[12];
+
+/** Offset 0x0220 - ISH UART Rx Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rx pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Rx, byte1 for UART1
+ Rx, and so on.
+**/
+ UINT8 IshUartRxPadTermination[3];
+
+/** Offset 0x0223 - ISH UART Tx Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Tx pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Tx, byte1 for UART1
+ Tx, and so on.
+**/
+ UINT8 IshUartTxPadTermination[3];
+
+/** Offset 0x0226 - ISH UART Rts Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Rts pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Rts, byte1 for UART1
+ Rts, and so on.
+**/
+ UINT8 IshUartRtsPadTermination[3];
+
+/** Offset 0x0229 - ISH UART Rts Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo UART#N Cts pads termination
+ respectively. #N-byte for each controller, byte0 for UART0 Cts, byte1 for UART1
+ Cts, and so on.
+**/
+ UINT8 IshUartCtsPadTermination[3];
+
+/** Offset 0x022C - ISH I2C SDA Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Sda pads termination
+ respectively. #N-byte for each controller, byte0 for I2C0 Sda, byte1 for I2C1 Sda,
+ and so on.
+**/
+ UINT8 IshI2cSdaPadTermination[3];
+
+/** Offset 0x022F - ISH I2C SCL Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C#N Scl pads termination
+ respectively. #N-byte for each controller, byte0 for I2C0 Scl, byte1 for I2C1 Scl,
+ and so on.
+**/
+ UINT8 IshI2cSclPadTermination[3];
+
+/** Offset 0x0232 - ISH SPI MOSI Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Mosi pads termination
+ respectively. #N-byte for each controller, byte0 for SPI0 Mosi, byte1 for SPI1
+ Mosi, and so on.
+**/
+ UINT8 IshSpiMosiPadTermination[2];
+
+/** Offset 0x0234 - ISH SPI MISO Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Miso pads termination
+ respectively. #N-byte for each controller, byte0 for SPI0 Miso, byte1 for SPI1
+ Miso, and so on.
+**/
+ UINT8 IshSpiMisoPadTermination[2];
+
+/** Offset 0x0236 - ISH SPI CLK Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Clk pads termination
+ respectively. #N-byte for each controller, byte0 for SPI0 Clk, byte1 for SPI1 Clk,
+ and so on.
+**/
+ UINT8 IshSpiClkPadTermination[2];
+
+/** Offset 0x0238 - ISH SPI CS#N Pad termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo SPI#N Cs#M pads termination
+ respectively. N*M-byte for each controller, byte0 for SPI0 Cs0, byte1 for SPI1
+ Cs1, SPI1 Cs0, byte2, SPI1 Cs1, byte3
+**/
+ UINT8 IshSpiCsPadTermination[4];
+
+/** Offset 0x023C - Enable PCH ISH SPI Cs#N pins assigned
+ Set if ISH SPI Cs#N pins are to be enabled by BIOS. 0: Disable; 1: Enable. N-Cs
+ number: 0-1
+**/
+ UINT8 PchIshSpiCsEnable[4];
+
+/** Offset 0x0240 - Enable PCH ISH SPI Cs0 pins assigned
+ Set if ISH SPI Cs0 pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiCs0Enable[1];
+
+/** Offset 0x0241 - Enable PCH ISH SPI pins assigned
+ Set if ISH SPI native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshSpiEnable[1];
+
+/** Offset 0x0242 - Enable PCH ISH UART pins assigned
+ Set if ISH UART native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshUartEnable[2];
+
+/** Offset 0x0244 - Enable PCH ISH I2C pins assigned
+ Set if ISH I2C native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshI2cEnable[3];
+
+/** Offset 0x0247 - Enable PCH ISH GP pins assigned
+ Set if ISH GP native pins are to be enabled by BIOS. 0: Disable; 1: Enable.
+**/
+ UINT8 PchIshGpEnable[12];
+
+/** Offset 0x0253 - PCH ISH PDT Unlock Msg
+ 0: False; 1: True.
+ $EN_DIS
+**/
+ UINT8 PchIshPdtUnlock;
+
+/** Offset 0x0254 - Reserved
+**/
+ UINT8 Reserved16;
+
+/** Offset 0x0255 - End of Post message
+ Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
+ EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
+ 0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
+**/
+ UINT8 EndOfPostMessage;
+
+/** Offset 0x0256 - D0I3 Setting for HECI Disable
+ Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
+ HECI devices
+ $EN_DIS
+**/
+ UINT8 DisableD0I3SettingForHeci;
+
+/** Offset 0x0257 - Mctp Broadcast Cycle
+ Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 MctpBroadcastCycle;
+
+/** Offset 0x0258 - ME Unconfig on RTC clear
+ 0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
+ 2: Cmos is clear, status unkonwn. 3: Reserved
+ 0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
+ is clear, 3: Reserved
+**/
+ UINT8 MeUnconfigOnRtcClear;
+
+/** Offset 0x0259 - Reserved
+**/
+ UINT8 Reserved17[27];
+
+/** Offset 0x0274 - Power button debounce configuration
+ Debounce time for PWRBTN in microseconds. For values not supported by HW, they will
+ be rounded down to closest supported on. 0: disable, 250-1024000us: supported range
+**/
+ UINT32 PmcPowerButtonDebounce;
+
+/** Offset 0x0278 - PCH USB2 PHY Power Gating enable
+ 1: Will enable USB2 PHY SUS Well Power Gating, 0: Will not enable PG of USB2 PHY
+ Sus Well PG
+ $EN_DIS
+**/
+ UINT8 PmcUsb2PhySusPgEnable;
+
+/** Offset 0x0279 - VRAlert# Pin
+ When VRAlert# feature pin is enabled and its state is '0', the PMC requests throttling
+ to a T3 Tstate to the PCH throttling unit.. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchPmVrAlert;
+
+/** Offset 0x027A - ModPHY SUS Power Domain Dynamic Gating
+ Enable/Disable ModPHY SUS Power Domain Dynamic Gating. Setting not supported on
+ PCH-H. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcModPhySusPgEnable;
+
+/** Offset 0x027B - V1p05-PHY supply external FET control
+ Enable/Disable control using EXT_PWR_GATE# pin of external FET to power gate v1p05-PHY
+ supply. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcV1p05PhyExtFetControlEn;
+
+/** Offset 0x027C - V1p05-IS supply external FET control
+ Enable/Disable control using EXT_PWR_GATE2# pin of external FET to power gate v1p05-IS
+ supply. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PmcV1p05IsExtFetControlEn;
+
+/** Offset 0x027D - PCH Pm PME_B0_S5_DIS
+ When cleared (default), wake events from PME_B0_STS are allowed in S5 if PME_B0_EN = 1.
+ $EN_DIS
+**/
+ UINT8 PchPmPmeB0S5Dis;
+
+/** Offset 0x027E - PCH Pm Wol Enable Override
+ Corresponds to the WOL Enable Override bit in the General PM Configuration B (GEN_PMCON_B) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolEnableOverride;
+
+/** Offset 0x027F - Reserved
+**/
+ UINT8 Reserved18;
+
+/** Offset 0x0280 - PCH Pm Slp S3 Min Assert
+ SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
+**/
+ UINT8 PchPmSlpS3MinAssert;
+
+/** Offset 0x0281 - PCH Pm Slp S4 Min Assert
+ SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
+**/
+ UINT8 PchPmSlpS4MinAssert;
+
+/** Offset 0x0282 - PCH Pm Slp Sus Min Assert
+ SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
+**/
+ UINT8 PchPmSlpSusMinAssert;
+
+/** Offset 0x0283 - PCH Pm Slp A Min Assert
+ SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
+**/
+ UINT8 PchPmSlpAMinAssert;
+
+/** Offset 0x0284 - PCH Pm Slp Strch Sus Up
+ Enable SLP_X Stretching After SUS Well Power Up.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpStrchSusUp;
+
+/** Offset 0x0285 - PCH Pm Slp Lan Low Dc
+ Enable/Disable SLP_LAN# Low on DC Power.
+ $EN_DIS
+**/
+ UINT8 PchPmSlpLanLowDc;
+
+/** Offset 0x0286 - PCH Pm Pwr Btn Override Period
+ PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
+**/
+ UINT8 PchPmPwrBtnOverridePeriod;
+
+/** Offset 0x0287 - PCH Pm Disable Native Power Button
+ Power button native mode disable.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableNativePowerButton;
+
+/** Offset 0x0288 - PCH Pm ME_WAKE_STS
+ Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmMeWakeSts;
+
+/** Offset 0x0289 - PCH Pm WOL_OVR_WK_STS
+ Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
+ $EN_DIS
+**/
+ UINT8 PchPmWolOvrWkSts;
+
+/** Offset 0x028A - PCH Pm Reset Power Cycle Duration
+ Could be customized in the unit of second. Please refer to EDS for all support settings.
+ 0 is default, 1 is 1 second, 2 is 2 seconds, ...
+**/
+ UINT8 PchPmPwrCycDur;
+
+/** Offset 0x028B - PCH Pm Pcie Pll Ssc
+ Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
+ BIOS override.
+**/
+ UINT8 PchPmPciePllSsc;
+
+/** Offset 0x028C - Enable TCO timer.
+ When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
+ huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
+ emulation must be enabled, and WDAT table must not be exposed to the OS.
+ $EN_DIS
+**/
+ UINT8 EnableTcoTimer;
+
+/** Offset 0x028D - Enable PS_ON.
+ PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
+ target that will be required by the California Energy Commission (CEC). When FALSE,
+ PS_ON is to be disabled.
+ $EN_DIS
+**/
+ UINT8 PsOnEnable;
+
+/** Offset 0x028E - Pmc Cpu C10 Gate Pin Enable
+ Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
+ and VccSTG rails instead of SLP_S0# pin.
+ $EN_DIS
+**/
+ UINT8 PmcCpuC10GatePinEnable;
+
+/** Offset 0x028F - OS IDLE Mode Enable
+ Enable/Disable OS Idle Mode
+ $EN_DIS
+**/
+ UINT8 PmcOsIdleEnable;
+
+/** Offset 0x0290 - S0ix Auto-Demotion
+ Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
+ $EN_DIS
+**/
+ UINT8 PchS0ixAutoDemotion;
+
+/** Offset 0x0291 - Latch Events C10 Exit
+ When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
+ captured on C10 exit (instead of C10 entry which is default)
+ $EN_DIS
+**/
+ UINT8 PchPmLatchEventsC10Exit;
+
+/** Offset 0x0292 - PCH Energy Reporting
+ Disable/Enable PCH to CPU energy report feature.
+ $EN_DIS
+**/
+ UINT8 PchPmDisableEnergyReport;
+
+/** Offset 0x0293 - Low Power Mode Enable/Disable config mask
+ Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
+ to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
+ LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
+**/
+ UINT8 PmcLpmS0ixSubStateEnableMask;
+
+/** Offset 0x0294 - Reserved
+**/
+ UINT8 Reserved19;
+
+/** Offset 0x0295 - PMC C10 dynamic threshold dajustment enable
+ Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
+ $EN_DIS
+**/
+ UINT8 PmcC10DynamicThresholdAdjustment;
+
+/** Offset 0x0296 - Enable LOCKDOWN BIOS LOCK
+ Enable the BIOS Lock feature and set EISS bit (D31:F5:RegDCh[5]) for the BIOS region
+ protection.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosLock;
+
+/** Offset 0x0297 - Enable LOCKDOWN SMI
+ Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
+ $EN_DIS
+**/
+ UINT8 PchLockDownGlobalSmi;
+
+/** Offset 0x0298 - Enable LOCKDOWN BIOS Interface
+ Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
+ $EN_DIS
+**/
+ UINT8 PchLockDownBiosInterface;
+
+/** Offset 0x0299 - Unlock all GPIO pads
+ Force all GPIO pads to be unlocked for debug purpose.
+ $EN_DIS
+**/
+ UINT8 PchUnlockGpioPads;
+
+/** Offset 0x029A - PCH Flash Protection Ranges Write Enble
+ Write or erase is blocked by hardware.
+**/
+ UINT8 PchWriteProtectionEnable[5];
+
+/** Offset 0x029F - PCH Flash Protection Ranges Read Enble
+ Read is blocked by hardware.
+**/
+ UINT8 PchReadProtectionEnable[5];
+
+/** Offset 0x02A4 - PCH Protect Range Limit
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for
+ limit comparison.
+**/
+ UINT16 PchProtectedRangeLimit[5];
+
+/** Offset 0x02AE - PCH Protect Range Base
+ Left shifted address by 12 bits with address bits 11:0 are assumed to be 0.
+**/
+ UINT16 PchProtectedRangeBase[5];
+
+/** Offset 0x02B8 - PCIe PTM enable/disable
+ Enable/disable Precision Time Measurement for PCIE Root Ports.
+**/
+ UINT8 PciePtm[28];
+
+/** Offset 0x02D4 - PCH PCIe root port connection type
+ 0: built-in device, 1:slot
+**/
+ UINT8 PcieRpSlotImplemented[28];
+
+/** Offset 0x02F0 - PCIE RP Access Control Services Extended Capability
+ Enable/Disable PCIE RP Access Control Services Extended Capability
+**/
+ UINT8 PcieRpAcsEnabled[28];
+
+/** Offset 0x030C - PCIE RP Clock Power Management
+ Enable/Disable PCIE RP Clock Power Management, even if disabled, CLKREQ# signal
+ can still be controlled by L1 PM substates mechanism
+**/
+ UINT8 PcieRpEnableCpm[28];
+
+/** Offset 0x0328 - PCIE RP Detect Timeout Ms
+ The number of milliseconds within 0~65535 in reference code will wait for link to
+ exit Detect state for enabled ports before assuming there is no device and potentially
+ disabling the port.
+**/
+ UINT16 PcieRpDetectTimeoutMs[24];
+
+/** Offset 0x0358 - Enable PCIE RP HotPlug
+ Indicate whether the root port is hot plug available.
+**/
+ UINT8 PcieRpHotPlug[28];
+
+/** Offset 0x0374 - Enable PCIE RP Pm Sci
+ Indicate whether the root port power manager SCI is enabled.
+**/
+ UINT8 PcieRpPmSci[28];
+
+/** Offset 0x0390 - Enable PCIE RP Transmitter Half Swing
+ Indicate whether the Transmitter Half Swing is enabled.
+**/
+ UINT8 PcieRpTransmitterHalfSwing[28];
+
+/** Offset 0x03AC - Enable PCIE RP Clk Req Detect
+ Probe CLKREQ# signal before enabling CLKREQ# based power management.
+**/
+ UINT8 PcieRpClkReqDetect[28];
+
+/** Offset 0x03C8 - PCIE RP Advanced Error Report
+ Indicate whether the Advanced Error Reporting is enabled.
+**/
+ UINT8 PcieRpAdvancedErrorReporting[28];
+
+/** Offset 0x03E4 - PCIE RP Unsupported Request Report
+ Indicate whether the Unsupported Request Report is enabled.
+**/
+ UINT8 PcieRpUnsupportedRequestReport[28];
+
+/** Offset 0x0400 - PCIE RP Fatal Error Report
+ Indicate whether the Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpFatalErrorReport[28];
+
+/** Offset 0x041C - PCIE RP No Fatal Error Report
+ Indicate whether the No Fatal Error Report is enabled.
+**/
+ UINT8 PcieRpNoFatalErrorReport[28];
+
+/** Offset 0x0438 - PCIE RP Correctable Error Report
+ Indicate whether the Correctable Error Report is enabled.
+**/
+ UINT8 PcieRpCorrectableErrorReport[28];
+
+/** Offset 0x0454 - PCIE RP System Error On Fatal Error
+ Indicate whether the System Error on Fatal Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnFatalError[28];
+
+/** Offset 0x0470 - PCIE RP System Error On Non Fatal Error
+ Indicate whether the System Error on Non Fatal Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnNonFatalError[28];
+
+/** Offset 0x048C - PCIE RP System Error On Correctable Error
+ Indicate whether the System Error on Correctable Error is enabled.
+**/
+ UINT8 PcieRpSystemErrorOnCorrectableError[28];
+
+/** Offset 0x04A8 - PCIE RP Max Payload
+ Max Payload Size supported, Default 256B, see enum PCH_PCIE_MAX_PAYLOAD.
+**/
+ UINT8 PcieRpMaxPayload[28];
+
+/** Offset 0x04C4 - PCIE RP Pcie Speed
+ Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see:
+ PCIE_SPEED).
+**/
+ UINT8 PcieRpPcieSpeed[28];
+
+/** Offset 0x04E0 - PCIE RP Physical Slot Number
+ Indicates the slot number for the root port. Default is the value as root port index.
+**/
+ UINT8 PcieRpPhysicalSlotNumber[28];
+
+/** Offset 0x04FC - PCIE RP Completion Timeout
+ The root port completion timeout(see: PCIE_COMPLETION_TIMEOUT). Default is PchPcieCompletionTO_Default.
+**/
+ UINT8 PcieRpCompletionTimeout[28];
+
+/** Offset 0x0518 - PCIE RP Aspm
+ The ASPM configuration of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is
+ PchPcieAspmAutoConfig.
+**/
+ UINT8 PcieRpAspm[28];
+
+/** Offset 0x0534 - Reserved
+**/
+ UINT8 Reserved20[28];
+
+/** Offset 0x0550 - PCIE RP L1 Substates
+ The L1 Substates configuration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL).
+ Default is PchPcieL1SubstatesL1_1_2.
+**/
+ UINT8 PcieRpL1Substates[28];
+
+/** Offset 0x056C - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 PcieRpLtrEnable[28];
+
+/** Offset 0x0588 - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 PcieRpLtrConfigLock[28];
+
+/** Offset 0x05A4 - PCIE RP override default settings for EQ
+ Choose PCIe EQ method
+ $EN_DIS
+**/
+ UINT8 PcieEqOverrideDefault[12];
+
+/** Offset 0x05B0 - Reserved
+**/
+ UINT8 Reserved21[1525];
+
+/** Offset 0x0BA5 - PCIE RP Enable Peer Memory Write
+ This member describes whether Peer Memory Writes are enabled on the platform.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePeerMemoryWrite[12];
+
+/** Offset 0x0BB1 - Assertion on Link Down GPIOs
+ GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down
+ GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs
+ 0:Disable, 1:Enable
+**/
+ UINT8 PcieRpLinkDownGpios[12];
+
+/** Offset 0x0BBD - PCIE Compliance Test Mode
+ Compliance Test Mode shall be enabled when using Compliance Load Board.
+ $EN_DIS
+**/
+ UINT8 PcieComplianceTestMode;
+
+/** Offset 0x0BBE - PCIE Rp Function Swap
+ Allows BIOS to use root port function number swapping when root port of function
+ 0 is disabled.
+ $EN_DIS
+**/
+ UINT8 PcieRpFunctionSwap;
+
+/** Offset 0x0BBF - Reserved
+**/
+ UINT8 Reserved22[12];
+
+/** Offset 0x0BCB - PCIe RootPort Power Gating
+ Describes whether the PCI Express Power Gating for each root port is enabled by
+ platform modules. 0: Disable; 1: Enable(Default).
+ $EN_DIS
+**/
+ UINT8 PciePowerGating[12];
+
+/** Offset 0x0BD7 - Reserved
+**/
+ UINT8 Reserved23[49];
+
+/** Offset 0x0C08 - PCIE RP Ltr Max Snoop Latency
+ Latency Tolerance Reporting, Max Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxSnoopLatency[24];
+
+/** Offset 0x0C38 - PCIE RP Ltr Max No Snoop Latency
+ Latency Tolerance Reporting, Max Non-Snoop Latency.
+**/
+ UINT16 PcieRpLtrMaxNoSnoopLatency[24];
+
+/** Offset 0x0C68 - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMode[28];
+
+/** Offset 0x0C84 - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpSnoopLatencyOverrideMultiplier[28];
+
+/** Offset 0x0CA0 - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 PcieRpSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0CD0 - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMode[28];
+
+/** Offset 0x0CEC - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[28];
+
+/** Offset 0x0D08 - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 PcieRpNonSnoopLatencyOverrideValue[24];
+
+/** Offset 0x0D38 - PCIE RP Slot Power Limit Scale
+ Specifies scale used for slot power limit value. Leave as 0 to set to default.
+**/
+ UINT8 PcieRpSlotPowerLimitScale[28];
+
+/** Offset 0x0D54 - PCIE RP Slot Power Limit Value
+ Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
+**/
+ UINT16 PcieRpSlotPowerLimitValue[24];
+
+/** Offset 0x0D84 - PCIE RP Enable Port8xh Decode
+ This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
+ 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PcieEnablePort8xhDecode;
+
+/** Offset 0x0D85 - PCIE Port8xh Decode Port Index
+ The Index of PCIe Port that is selected for Port8xh Decode (1 Based).
+**/
+ UINT8 PchPciePort8xhDecodePortIndex;
+
+/** Offset 0x0D86 - Reserved
+**/
+ UINT8 Reserved24[114];
+
+/** Offset 0x0DF8 - SPIn Device Mode
+ Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
+ modes: 0:LpssSpiDisabled, 1:LpssSpiPci, 2:LpssSpiHidden
+**/
+ UINT8 SerialIoLpssSpiMode[7];
+
+/** Offset 0x0DFF - Reserved
+**/
+ UINT8 Reserved25[85];
+
+/** Offset 0x0E54 - SPIn Default Chip Select Mode HW/SW
+ Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
+ SPI1, ... Available options: 0:HW, 1:SW
+**/
+ UINT8 SerialIoLpssSpiCsMode[7];
+
+/** Offset 0x0E5B - SPIn Default Chip Select State Low/High
+ Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
+ Available options: 0:Low, 1:High
+**/
+ UINT8 SerialIoLpssSpiCsState[7];
+
+/** Offset 0x0E62 - UARTn Device Mode
+ Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
+ modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
+ 4:SerialIoUartSkipInit
+**/
+ UINT8 SerialIoUartMode[7];
+
+/** Offset 0x0E69 - Reserved
+**/
+ UINT8 Reserved26[3];
+
+/** Offset 0x0E6C - Default BaudRate for each Serial IO UART
+ Set default BaudRate Supported from 0 - default to 6000000
+**/
+ UINT32 SerialIoUartBaudRate[7];
+
+/** Offset 0x0E88 - Default ParityType for each Serial IO UART
+ Set default Parity. 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
+**/
+ UINT8 SerialIoUartParity[7];
+
+/** Offset 0x0E8F - Default DataBits for each Serial IO UART
+ Set default word length. 0: Default, 5,6,7,8
+**/
+ UINT8 SerialIoUartDataBits[7];
+
+/** Offset 0x0E96 - Default StopBits for each Serial IO UART
+ Set default stop bits. 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3:
+ TwoStopBits
+**/
+ UINT8 SerialIoUartStopBits[7];
+
+/** Offset 0x0E9D - Power Gating mode for each Serial IO UART that works in COM mode
+ Set Power Gating. 0: Disabled, 1: Enabled, 2: Auto
+**/
+ UINT8 SerialIoUartPowerGating[7];
+
+/** Offset 0x0EA4 - Enable Dma for each Serial IO UART that supports it
+ Set DMA/PIO mode. 0: Disabled, 1: Enabled
+**/
+ UINT8 SerialIoUartDmaEnable[7];
+
+/** Offset 0x0EAB - Enables UART hardware flow control, CTS and RTS lines
+ Enables UART hardware flow control, CTS and RTS lines.
+**/
+ UINT8 SerialIoUartAutoFlow[7];
+
+/** Offset 0x0EB2 - Reserved
+**/
+ UINT8 Reserved27[2];
+
+/** Offset 0x0EB4 - SerialIoUartRtsPinMuxPolicy
+ Select SerialIo Uart Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
+ for possible values.
+**/
+ UINT32 SerialIoUartRtsPinMuxPolicy[7];
+
+/** Offset 0x0ED0 - SerialIoUartRxPinMuxPolicy
+ Select SerialIo Uart Rx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RX* for
+ possible values.
+**/
+ UINT32 SerialIoUartRxPinMuxPolicy[7];
+
+/** Offset 0x0EEC - SerialIoUartTxPinMuxPolicy
+ Select SerialIo Uart Tx pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_TX* for
+ possible values.
+**/
+ UINT32 SerialIoUartTxPinMuxPolicy[7];
+
+/** Offset 0x0F08 - Serial IO UART DBG2 table
+ Enable or disable Serial Io UART DBG2 table, default is Disable; <b>0: Disable;</b>
+ 1: Enable.
+**/
+ UINT8 SerialIoUartDbg2[7];
+
+/** Offset 0x0F0F - I2Cn Device Mode
+ Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
+ modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
+**/
+ UINT8 SerialIoI2cMode[8];
+
+/** Offset 0x0F17 - Reserved
+**/
+ UINT8 Reserved28;
+
+/** Offset 0x0F18 - Serial IO I2C SDA Pin Muxing
+ Select SerialIo I2c Sda pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SDA* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSdaPinMux[8];
+
+/** Offset 0x0F38 - Serial IO I2C SCL Pin Muxing
+ Select SerialIo I2c Scl pin muxing. Refer to GPIO_*_MUXING_SERIALIO_I2Cx_SCL* for
+ possible values.
+**/
+ UINT32 PchSerialIoI2cSclPinMux[8];
+
+/** Offset 0x0F58 - PCH SerialIo I2C Pads Termination
+ 0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
+ 0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,... pads termination
+ respectively. One byte for each controller, byte0 for I2C0, byte1 for I2C1, and so on.
+**/
+ UINT8 PchSerialIoI2cPadsTermination[8];
+
+/** Offset 0x0F60 - Reserved
+**/
+ UINT8 Reserved29[148];
+
+/** Offset 0x0FF4 - TypeC port GPIO setting
+ GPIO Ping number for Type C Aux orientation setting, use the GpioPad that is defined
+ in GpioPinsXXXH.h and GpioPinsXXXLp.h as argument.(XXX is platform name, Ex: Lnl
+ = LunarLake)
+**/
+ UINT32 IomTypeCPortPadCfg[12];
+
+/** Offset 0x1024 - CPU USB3 Port Over Current Pin
+ Describe the specific over current pin number of USBC Port N.
+**/
+ UINT8 CpuUsb3OverCurrentPin[10];
+
+/** Offset 0x102E - Enable D3 Cold in TCSS
+ This policy will enable/disable D3 cold support in IOM
+ $EN_DIS
+**/
+ UINT8 D3ColdEnable;
+
+/** Offset 0x102F - TC State in TCSS
+ This TC C-State Limit in IOM
+**/
+ UINT8 TcCstateLimit;
+
+/** Offset 0x1030 - Reserved
+**/
+ UINT8 Reserved30[2];
+
+/** Offset 0x1032 - Enable/Disable PMC-PD Solution
+ This policy will enable/disable PMC-PD Solution vs EC-TCPC Solution
+ $EN_DIS
+**/
+ UINT8 PmcPdEnable;
+
+/** Offset 0x1033 - Reserved
+**/
+ UINT8 Reserved31;
+
+/** Offset 0x1034 - TCSS Aux Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssAuxOri;
+
+/** Offset 0x1036 - TCSS HSL Orientation Override Enable
+ Bits 0, 2, ... 10 control override enables, bits 1, 3, ... 11 control overrides
+**/
+ UINT16 TcssHslOri;
+
+/** Offset 0x1038 - TCSS USB Port Enable
+ Bits 0, 1, ... max Type C port control enables
+**/
+ UINT8 UsbTcPortEn;
+
+/** Offset 0x1039 - VCCST request for IOM
+ This policy will enable/disable VCCST and also decides if message would be replayed in S4/S5
+ $EN_DIS
+**/
+ UINT8 VccSt;
+
+/** Offset 0x103A - Enable/Disable PTM
+ This policy will enable/disable Precision Time Measurement for TCSS PCIe Root Ports
+ $EN_DIS
+**/
+ UINT8 PtmEnabled[4];
+
+/** Offset 0x103E - PCIE RP Ltr Enable
+ Latency Tolerance Reporting Mechanism.
+**/
+ UINT8 SaPcieItbtRpLtrEnable[4];
+
+/** Offset 0x1042 - PCIE RP Snoop Latency Override Mode
+ Latency Tolerance Reporting, Snoop Latency Override Mode.
+**/
+ UINT8 SaPcieItbtRpSnoopLatencyOverrideMode[4];
+
+/** Offset 0x1046 - PCIE RP Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Snoop Latency Override Multiplier.
+**/
+ UINT8 SaPcieItbtRpSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x104A - PCIE RP Snoop Latency Override Value
+ Latency Tolerance Reporting, Snoop Latency Override Value.
+**/
+ UINT16 SaPcieItbtRpSnoopLatencyOverrideValue[4];
+
+/** Offset 0x1052 - PCIE RP Non Snoop Latency Override Mode
+ Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
+**/
+ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMode[4];
+
+/** Offset 0x1056 - PCIE RP Non Snoop Latency Override Multiplier
+ Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
+**/
+ UINT8 SaPcieItbtRpNonSnoopLatencyOverrideMultiplier[4];
+
+/** Offset 0x105A - PCIE RP Non Snoop Latency Override Value
+ Latency Tolerance Reporting, Non-Snoop Latency Override Value.
+**/
+ UINT16 SaPcieItbtRpNonSnoopLatencyOverrideValue[4];
+
+/** Offset 0x1062 - Force LTR Override
+ Force LTR Override.
+**/
+ UINT8 SaPcieItbtRpForceLtrOverride[4];
+
+/** Offset 0x1066 - PCIE RP Ltr Config Lock
+ 0: Disable; 1: Enable.
+**/
+ UINT8 SaPcieItbtRpLtrConfigLock[4];
+
+/** Offset 0x106A - Reserved
+**/
+ UINT8 Reserved32[4];
+
+/** Offset 0x106E - Touch Host Controller Assignment
+ Assign THC 0x0:ThcAssignmentNone, 0x1:ThcAssignmentThc0, 0x2:ThcAssignmentThc1
+**/
+ UINT8 ThcAssignment[2];
+
+/** Offset 0x1070 - Reserved
+**/
+ UINT8 Reserved33[349];
+
+/** Offset 0x11CD - PCHHOT# pin
+ Enable PCHHOT# pin assertion when temperature is higher than PchHotLevel. 0: disable, 1: enable
+ $EN_DIS
+**/
+ UINT8 PchHotEnable;
+
+/** Offset 0x11CE - Thermal Throttling Custimized T0Level Value
+ Custimized T0Level value.
+**/
+ UINT16 PchT0Level;
+
+/** Offset 0x11D0 - Thermal Throttling Custimized T1Level Value
+ Custimized T1Level value.
+**/
+ UINT16 PchT1Level;
+
+/** Offset 0x11D2 - Thermal Throttling Custimized T2Level Value
+ Custimized T2Level value.
+**/
+ UINT16 PchT2Level;
+
+/** Offset 0x11D4 - Enable The Thermal Throttle
+ Enable the thermal throttle function.
+ $EN_DIS
+**/
+ UINT8 PchTTEnable;
+
+/** Offset 0x11D5 - PMSync State 13
+ When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
+ at least T2 state.
+ $EN_DIS
+**/
+ UINT8 PchTTState13Enable;
+
+/** Offset 0x11D6 - Thermal Throttle Lock
+ Thermal Throttle Lock.
+ $EN_DIS
+**/
+ UINT8 PchTTLock;
+
+/** Offset 0x11D7 - Thermal Throttling Suggested Setting
+ Thermal Throttling Suggested Setting.
+ $EN_DIS
+**/
+ UINT8 TTSuggestedSetting;
+
+/** Offset 0x11D8 - Thermal Device Temperature
+ Decides the temperature.
+**/
+ UINT16 PchTemperatureHotLevel;
+
+/** Offset 0x11DA
+**/
+ UINT8 PchTsnEnable[4];
+
+/** Offset 0x11DE - Enable TSN Multi-VC
+ Enable/disable Multi Virtual Channels(VC) in TSN.
+ $EN_DIS
+**/
+ UINT8 PchTsnMultiVcEnable;
+
+/** Offset 0x11DF - Reserved
+**/
+ UINT8 Reserved34[33];
+
+/** Offset 0x1200 - Enable USB2 ports
+ Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb20Enable[16];
+
+/** Offset 0x1210 - Enable USB3 ports
+ Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
+ port1, and so on.
+**/
+ UINT8 PortUsb30Enable[10];
+
+/** Offset 0x121A - Enable xDCI controller
+ Enable/disable to xDCI controller.
+ $EN_DIS
+**/
+ UINT8 XdciEnable;
+
+/** Offset 0x121B - USB PDO Programming
+ Enable/disable PDO programming for USB in PEI phase. Disabling will allow for programming
+ during later phase. 1: enable, 0: disable
+ $EN_DIS
+**/
+ UINT8 UsbPdoProgramming;
+
+/** Offset 0x121C - Reserved
+**/
+ UINT8 Reserved35;
+
+/** Offset 0x121D - PCH USB OverCurrent mapping enable
+ 1: Will program USB OC pin mapping in xHCI controller memory, 0: Will clear OC pin
+ mapping allow for NOA usage of OC pins
+ $EN_DIS
+**/
+ UINT8 PchUsbOverCurrentEnable;
+
+/** Offset 0x121E - USB2 Port Over Current Pin
+ Describe the specific over current pin number of USB 2.0 Port N.
+**/
+ UINT8 Usb2OverCurrentPin[16];
+
+/** Offset 0x122E - USB3 Port Over Current Pin
+ Describe the specific over current pin number of USB 3.0 Port N.
+**/
+ UINT8 Usb3OverCurrentPin[10];
+
+/** Offset 0x1238 - Enable xHCI LTR override
+ Enables override of recommended LTR values for xHCI
+ $EN_DIS
+**/
+ UINT8 PchUsbLtrOverrideEnable;
+
+/** Offset 0x1239 - Reserved
+**/
+ UINT8 Reserved36[3];
+
+/** Offset 0x123C - xHCI High Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrHighIdleTimeOverride;
+
+/** Offset 0x1240 - xHCI Medium Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrMediumIdleTimeOverride;
+
+/** Offset 0x1244 - xHCI Low Idle Time LTR override
+ Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
+**/
+ UINT32 PchUsbLtrLowIdleTimeOverride;
+
+/** Offset 0x1248 - USB2 Port Reset Message Enable
+ 0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must
+ be enable for USB2 Port those are paired with CPU XHCI Port
+**/
+ UINT8 PortResetMessageEnable[16];
+
+/** Offset 0x1258 - PCH USB OverCurrent mapping lock enable
+ If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
+ that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
+ $EN_DIS
+**/
+ UINT8 PchXhciOcLock;
+
+/** Offset 0x1259 - USB Per Port HS Preemphasis Bias
+ USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
+**/
+ UINT8 Usb2PhyPetxiset[16];
+
+/** Offset 0x1269 - USB Per Port HS Transmitter Bias
+ USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
+ 100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
+**/
+ UINT8 Usb2PhyTxiset[16];
+
+/** Offset 0x1279 - USB Per Port HS Transmitter Emphasis
+ USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
+ 10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
+**/
+ UINT8 Usb2PhyPredeemp[16];
+
+/** Offset 0x1289 - USB Per Port Half Bit Pre-emphasis
+ USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
+ One byte for each port.
+**/
+ UINT8 Usb2PhyPehalfbit[16];
+
+/** Offset 0x1299 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
+ Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmphEnable[10];
+
+/** Offset 0x12A3 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
+ USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
+ <b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
+**/
+ UINT8 Usb3HsioTxDeEmph[10];
+
+/** Offset 0x12AD - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
+ Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
+ in arrary can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmpEnable[10];
+
+/** Offset 0x12B7 - USB 3.0 TX Output Downscale Amplitude Adjustment
+ USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
+ = 00h</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxDownscaleAmp[10];
+
+/** Offset 0x12C1
+**/
+ UINT8 PchUsb3HsioCtrlAdaptOffsetCfgEnable[10];
+
+/** Offset 0x12CB
+**/
+ UINT8 PchUsb3HsioFilterSelNEnable[10];
+
+/** Offset 0x12D5
+**/
+ UINT8 PchUsb3HsioFilterSelPEnable[10];
+
+/** Offset 0x12DF
+**/
+ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnResEnable[10];
+
+/** Offset 0x12E9
+**/
+ UINT8 PchUsb3HsioCtrlAdaptOffsetCfg[10];
+
+/** Offset 0x12F3
+**/
+ UINT8 PchUsb3HsioOlfpsCfgPullUpDwnRes[10];
+
+/** Offset 0x12FD
+**/
+ UINT8 PchUsb3HsioFilterSelN[10];
+
+/** Offset 0x1307
+**/
+ UINT8 PchUsb3HsioFilterSelP[10];
+
+/** Offset 0x1311 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate3UniqTranEnable[10];
+
+/** Offset 0x131B - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
+ = 4Ch</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate3UniqTran[10];
+
+/** Offset 0x1325 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate2UniqTranEnable[10];
+
+/** Offset 0x132F - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
+ <b>Default = 4Ch</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate2UniqTran[10];
+
+/** Offset 0x1339 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate1UniqTranEnable[10];
+
+/** Offset 0x1343 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
+ <b>Default = 4Ch</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate1UniqTran[10];
+
+/** Offset 0x134D - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+ Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
+ value in array can be between 0-1. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate0UniqTranEnable[10];
+
+/** Offset 0x1357 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+ USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
+ <b>Default = 4Ch</b>. One byte for each port.
+**/
+ UINT8 Usb3HsioTxRate0UniqTran[10];
+
+/** Offset 0x1361 - Reserved
+**/
+ UINT8 Reserved37[4];
+
+/** Offset 0x1365 - Enable/Disable NPU Device
+ Enable(Default): Enable NPU Device, Disable: Disable NPU Device
+ $EN_DIS
+**/
+ UINT8 NpuEnable;
+
+/** Offset 0x1366 - Enable LAN
+ Enable/disable LAN controller.
+ $EN_DIS
+**/
+ UINT8 PchLanEnable;
+
+/** Offset 0x1367 - Enable PCH Lan LTR capabilty of PCH internal LAN
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchLanLtrEnable;
+
+/** Offset 0x1368 - Reserved
+**/
+ UINT8 Reserved38;
+
+/** Offset 0x1369 - Skip Ssid Programming.
+ When set to TRUE, silicon code will not do any SSID programming and platform code
+ needs to handle that by itself properly.
+ $EN_DIS
+**/
+ UINT8 SiSkipSsidProgramming;
+
+/** Offset 0x136A - Change Default SVID
+ Change the default SVID used in FSP to programming internal devices. This is only
+ valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiCustomizedSvid;
+
+/** Offset 0x136C - Change Default SSID
+ Change the default SSID used in FSP to programming internal devices. This is only
+ valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiCustomizedSsid;
+
+/** Offset 0x136E - Reserved
+**/
+ UINT8 Reserved39[2];
+
+/** Offset 0x1370 - SVID SDID table Poniter.
+ The address of the table of SVID SDID to customize each SVID SDID entry. This is
+ only valid when SkipSsidProgramming is FALSE.
+**/
+ UINT64 SiSsidTablePtr;
+
+/** Offset 0x1378 - Number of ssid table.
+ SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
+ This is only valid when SkipSsidProgramming is FALSE.
+**/
+ UINT16 SiNumberOfSsidTableEntry;
+
+/** Offset 0x137A - Reserved
+**/
+ UINT8 Reserved40[10];
+
+/** Offset 0x1384 - LogoPixelHeight Address
+ Address of LogoPixelHeight
+**/
+ UINT32 LogoPixelHeight;
+
+/** Offset 0x1388 - LogoPixelWidth Address
+ Address of LogoPixelWidth
+**/
+ UINT32 LogoPixelWidth;
+
+/** Offset 0x138C - Reserved
+**/
+ UINT8 Reserved41[4];
+
+/** Offset 0x1390 - Blt Buffer Address
+ Address of Blt buffer
+**/
+ UINT64 BltBufferAddress;
+
+/** Offset 0x1398 - Graphics Configuration Ptr
+ Points to VBT
+**/
+ UINT64 GraphicsConfigPtr;
+
+/** Offset 0x13A0 - Enable/Disable SkipFspGop
+ Enable: Skip FSP provided GOP driver, Disable(Default): Use FSP provided GOP driver
+ $EN_DIS
+**/
+ UINT8 SkipFspGop;
+
+/** Offset 0x13A1 - Reserved
+**/
+ UINT8 Reserved42;
+
+/** Offset 0x13A2 - Enable/Disable IGFX RenderStandby
+ Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
+ $EN_DIS
+**/
+ UINT8 RenderStandby;
+
+/** Offset 0x13A3 - Reserved
+**/
+ UINT8 Reserved43[3];
+
+/** Offset 0x13A6 - Enable/Disable PavpEnable
+ Enable(Default): Enable PavpEnable, Disable: Disable PavpEnable
+ $EN_DIS
+**/
+ UINT8 PavpEnable;
+
+/** Offset 0x13A7 - Enable/Disable PeiGraphicsPeimInit
+ <b>Enable(Default):</b> FSP will initialize the framebuffer and provide it via EFI_PEI_GRAPHICS_INFO_HOB.
+ Disable: FSP will NOT initialize the framebuffer.
+ $EN_DIS
+**/
+ UINT8 PeiGraphicsPeimInit;
+
+/** Offset 0x13A8 - Reserved
+**/
+ UINT8 Reserved44[4];
+
+/** Offset 0x13AC - Intel Graphics VBT (Video BIOS Table) Size
+ Size of Internal Graphics VBT Image
+**/
+ UINT32 VbtSize;
+
+/** Offset 0x13B0 - Platform LID Status for LFP Displays.
+ LFP Display Lid Status (LID_STATUS enum): 0 (Default): LidClosed, 1: LidOpen.
+ 0: LidClosed, 1: LidOpen
+**/
+ UINT8 LidStatus;
+
+/** Offset 0x13B1 - Reserved
+**/
+ UINT8 Reserved45[11];
+
+/** Offset 0x13BC - Address of PCH_DEVICE_INTERRUPT_CONFIG table.
+ The address of the table of PCH_DEVICE_INTERRUPT_CONFIG.
+**/
+ UINT32 DevIntConfigPtr;
+
+/** Offset 0x13C0 - Number of DevIntConfig Entry
+ Number of Device Interrupt Configuration Entry. If this is not zero, the DevIntConfigPtr
+ must not be NULL.
+**/
+ UINT8 NumOfDevIntConfig;
+
+/** Offset 0x13C1 - Select GPIO IRQ Route
+ GPIO IRQ Select. The valid value is 14 or 15.
+**/
+ UINT8 GpioIrqRoute;
+
+/** Offset 0x13C2 - Select SciIrqSelect
+ SCI IRQ Select. The valid value is 9, 10, 11, and 20, 21, 22, 23 for APIC only.
+**/
+ UINT8 SciIrqSelect;
+
+/** Offset 0x13C3 - Select TcoIrqSelect
+ TCO IRQ Select. The valid value is 9, 10, 11, 20, 21, 22, 23.
+**/
+ UINT8 TcoIrqSelect;
+
+/** Offset 0x13C4 - Enable/Disable Tco IRQ
+ Enable/disable TCO IRQ
+ $EN_DIS
+**/
+ UINT8 TcoIrqEnable;
+
+/** Offset 0x13C5 - Reserved
+**/
+ UINT8 Reserved46[5];
+
+/** Offset 0x13CA - Mask to enable the usage of external V1p05 VR rail in specific S0ix or Sx states
+ Enable External V1P05 Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtV1p05RailEnabledStates;
+
+/** Offset 0x13CB - Mask to enable the platform configuration of external V1p05 VR rail
+ External V1P05 Rail Supported Configuration
+**/
+ UINT8 PchFivrExtV1p05RailSupportedVoltageStates;
+
+/** Offset 0x13CC - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
+ Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
+**/
+ UINT16 PchFivrExtV1p05RailVoltage;
+
+/** Offset 0x13CE - External V1P05 Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtV1p05RailIccMax;
+
+/** Offset 0x13CF - Mask to enable the usage of external Vnn VR rail in specific S0ix or Sx states
+ Enable External Vnn Rail in: BIT0:S0i1/S0i2, BIT1:S0i3, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtVnnRailEnabledStates;
+
+/** Offset 0x13D0 - Mask to enable the platform configuration of external Vnn VR rail
+ External Vnn Rail Supported Configuration
+**/
+ UINT8 PchFivrExtVnnRailSupportedVoltageStates;
+
+/** Offset 0x13D1 - Reserved
+**/
+ UINT8 Reserved47;
+
+/** Offset 0x13D2 - External Vnn Voltage Value that will be used in S0ix/Sx states
+ Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...), Default is set to 420
+**/
+ UINT16 PchFivrExtVnnRailVoltage;
+
+/** Offset 0x13D4 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+ Granularity of this setting is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtVnnRailIccMax;
+
+/** Offset 0x13D5 - Mask to enable the usage of external Vnn VR rail in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Enable External Vnn Rail in
+ Sx: BIT0-1:Reserved, BIT2:S3, BIT3:S4, BIT5:S5
+**/
+ UINT8 PchFivrExtVnnRailSxEnabledStates;
+
+/** Offset 0x13D6 - External Vnn Voltage Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
+ (0=0mV, 1=2.5mV, 2=5mV...)
+**/
+ UINT16 PchFivrExtVnnRailSxVoltage;
+
+/** Offset 0x13D8 - External Vnn Icc Max Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
+ is 1mA and maximal possible value is 200mA
+**/
+ UINT8 PchFivrExtVnnRailSxIccMax;
+
+/** Offset 0x13D9 - Transition time in microseconds from Low Current Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to low current mode voltage.
+**/
+ UINT8 PchFivrVccinAuxLowToHighCurModeVolTranTime;
+
+/** Offset 0x13DA - Transition time in microseconds from Retention Mode Voltage to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to retention mode voltage.
+**/
+ UINT8 PchFivrVccinAuxRetToHighCurModeVolTranTime;
+
+/** Offset 0x13DB - Transition time in microseconds from Retention Mode Voltage to Low Current Mode Voltage
+ This field has 1us resolution. When value is 0 PCH will not transition VCCIN_AUX
+ to retention mode voltage.
+**/
+ UINT8 PchFivrVccinAuxRetToLowCurModeVolTranTime;
+
+/** Offset 0x13DC - Transition time in microseconds from Off (0V) to High Current Mode Voltage
+ This field has 1us resolution. When value is 0 Transition to 0V is disabled.
+**/
+ UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
+
+/** Offset 0x13DE - FIVR Dynamic Power Management
+ Enable/Disable FIVR Dynamic Power Management.
+ $EN_DIS
+**/
+ UINT8 PchFivrDynPm;
+
+/** Offset 0x13DF - Reserved
+**/
+ UINT8 Reserved48;
+
+/** Offset 0x13E0 - External V1P05 Icc Max Value
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+**/
+ UINT16 PchFivrExtV1p05RailIccMaximum;
+
+/** Offset 0x13E2 - External Vnn Icc Max Value that will be used in S0ix/Sx states
+ Granularity of this setting is 1mA and maximal possible value is 500mA
+**/
+ UINT16 PchFivrExtVnnRailIccMaximum;
+
+/** Offset 0x13E4 - External Vnn Icc Max Value that will be used in Sx states
+ Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
+ is 1mA and maximal possible value is 500mA
+**/
+ UINT16 PchFivrExtVnnRailSxIccMaximum;
+
+/** Offset 0x13E6 - External V1P05 Control Ramp Timer value
+ Hold off time to be used when changing the v1p05_ctrl for external bypass value in us
+**/
+ UINT8 PchFivrExtV1p05RailCtrlRampTmr;
+
+/** Offset 0x13E7 - External VNN Control Ramp Timer value
+ Hold off time to be used when changing the vnn_ctrl for external bypass value in us
+**/
+ UINT8 PchFivrExtVnnRailCtrlRampTmr;
+
+/** Offset 0x13E8 - PCH Compatibility Revision ID
+ This member describes whether or not the CRID feature of PCH should be enabled.
+ $EN_DIS
+**/
+ UINT8 PchCrid;
+
+/** Offset 0x13E9 - PCH Legacy IO Low Latency Enable
+ Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchLegacyIoLowLatency;
+
+/** Offset 0x13EA - Reserved
+**/
+ UINT8 Reserved49;
+
+/** Offset 0x13EB - PCH Unlock SideBand access
+ The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
+ 3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
+ $EN_DIS
+**/
+ UINT8 PchSbAccessUnlock;
+
+/** Offset 0x13EC - Enable 8254 Static Clock Gating
+ Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
+ might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
+ legacy OS using 8254 timer. Also enable this while S0ix is enabled.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGating;
+
+/** Offset 0x13ED - Enable 8254 Static Clock Gating On S3
+ This is only applicable when Enable8254ClockGating is disabled. FSP will do the
+ 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
+ avoids the SMI requirement for the programming.
+ $EN_DIS
+**/
+ UINT8 Enable8254ClockGatingOnS3;
+
+/** Offset 0x13EE - Enable PCH Io Apic Entry 24-119
+ 0: Disable; 1: Enable.
+ $EN_DIS
+**/
+ UINT8 PchIoApicEntry24_119;
+
+/** Offset 0x13EF - PCH Io Apic ID
+ This member determines IOAPIC ID. Default is 0x02.
+**/
+ UINT8 PchIoApicId;
+
+/** Offset 0x13F0 - CNVi Configuration
+ This option allows for automatic detection of Connectivity Solution. [Auto Detection]
+ assumes that CNVi will be enabled when available, [Disable] allows for disabling CNVi.
+ 0:Disable, 1:Auto
+**/
+ UINT8 CnviMode;
+
+/** Offset 0x13F1 - CNVi Wi-Fi Core
+ Enable/Disable CNVi Wi-Fi Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviWifiCore;
+
+/** Offset 0x13F2 - CNVi BT Core
+ Enable/Disable CNVi BT Core, Default is ENABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtCore;
+
+/** Offset 0x13F3 - CNVi BT Interface
+ This option configures BT device interface to either USB/PCI
+ 1:USB, 2:PCI
+**/
+ UINT8 CnviBtInterface;
+
+/** Offset 0x13F4 - CNVi BT Audio Offload
+ Enable/Disable BT Audio Offload, Default is ENABLE. 0: DISABLE, 1: ENABLE
+ $EN_DIS
+**/
+ UINT8 CnviBtAudioOffload;
+
+/** Offset 0x13F5 - Reserved
+**/
+ UINT8 Reserved50[3];
+
+/** Offset 0x13F8 - CNVi RF_RESET pin muxing
+ Select CNVi RF_RESET# pin depending on board routing. LP/P/M: GPP_A8 = 0x2942E408(default)
+ or GPP_F4 = 0x194CE404. H/S: 0. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
+**/
+ UINT32 CnviRfResetPinMux;
+
+/** Offset 0x13FC - CNVi CLKREQ pin muxing
+ Select CNVi CLKREQ pin depending on board routing. LP/P/M: GPP_A9 = 0x3942E609(default)
+ or GPP_F5 = 0x394CE605. H/S: 0. Refer to GPIO_*_MUXING_CNVI_CRF_XTAL_CLKREQ_* in
+ GpioPins*.h.
+**/
+ UINT32 CnviClkreqPinMux;
+
+/** Offset 0x1400 - Reserved
+**/
+ UINT8 Reserved51;
+
+/** Offset 0x1401 - Enable Device 4
+ Enable/disable Device 4
+ $EN_DIS
+**/
+ UINT8 Device4Enable;
+
+/** Offset 0x1402 - Skip PAM regsiter lock
+ Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
+ PAM registers will be locked by RC
+ $EN_DIS
+**/
+ UINT8 SkipPamLock;
+
+/** Offset 0x1403 - Reserved
+**/
+ UINT8 Reserved52;
+
+/** Offset 0x1404 - PCH HDA Verb Table Entry Number
+ Number of Entries in Verb Table.
+**/
+ UINT8 PchHdaVerbTableEntryNum;
+
+/** Offset 0x1405 - Reserved
+**/
+ UINT8 Reserved53[3];
+
+/** Offset 0x1408 - PCH HDA Verb Table Pointer
+ Pointer to Array of pointers to Verb Table.
+**/
+ UINT64 PchHdaVerbTablePtr;
+
+/** Offset 0x1410 - PCH HDA Codec Sx Wake Capability
+ Capability to detect wake initiated by a codec in Sx
+**/
+ UINT8 PchHdaCodecSxWakeCapability;
+
+/** Offset 0x1411 - Enable Pme
+ Enable Azalia wake-on-ring.
+ $EN_DIS
+**/
+ UINT8 PchHdaPme;
+
+/** Offset 0x1412 - HD Audio Link Frequency
+ HDA Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 0: 6MHz, 1: 12MHz, 2: 24MHz.
+ 0: 6MHz, 1: 12MHz, 2: 24MHz
+**/
+ UINT8 PchHdaLinkFrequency;
+
+/** Offset 0x1413 - Reserved
+**/
+ UINT8 Reserved54[2];
+
+/** Offset 0x1415 - HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode
+ HD Audio Microphone Privacy applied for SoundWire Link number 0 in HW Mode: 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchHdaMicPrivacyHwModeSoundWire0;
+
+/** Offset 0x1416 - HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode
+ HD Audio Microphone Privacy applied for SoundWire Link number 1 in HW Mode: 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchHdaMicPrivacyHwModeSoundWire1;
+
+/** Offset 0x1417 - HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode
+ HD Audio Microphone Privacy applied for SoundWire Link number 2 in HW Mode: 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchHdaMicPrivacyHwModeSoundWire2;
+
+/** Offset 0x1418 - HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode
+ HD Audio Microphone Privacy applied for SoundWire Link number 3 in HW Mode: 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchHdaMicPrivacyHwModeSoundWire3;
+
+/** Offset 0x1419 - HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode
+ HD Audio Microphone Privacy applied for SoundWire Link number 4 in HW Mode: 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchHdaMicPrivacyHwModeSoundWire4;
+
+/** Offset 0x141A - HD Audio Microphone Privacy applied for Dmic in HW Mode
+ HD Audio Microphone Privacy applied for Dmic in HW Mode: 0: Disable, 1: Enable
+ $EN_DIS
+**/
+ UINT8 PchHdaMicPrivacyHwModeDmic;
+
+/** Offset 0x141B - Reserved
+**/
+ UINT8 Reserved55[13];
+
+/** Offset 0x1428 - Pointer to ChipsetInit Binary
+ ChipsetInit Binary Pointer.
+**/
+ UINT64 ChipsetInitBinPtr;
+
+/** Offset 0x1430 - Length of ChipsetInit Binary
+ ChipsetInit Binary Length.
+**/
+ UINT32 ChipsetInitBinLen;
+
+/** Offset 0x1434 - Reserved
+**/
+ UINT8 Reserved56[36];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@@ -80,11 +2315,11 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x0040
+/** Offset 0x1458
**/
- UINT8 UnusedUpdSpace1[6];
+ UINT8 UnusedUpdSpace35[6];
-/** Offset 0x0046
+/** Offset 0x145E
**/
UINT16 UpdTerminator;
} FSPS_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
index e01034875c..778a27d2b5 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/pantherlake/MemInfoHob.h
@@ -22,6 +22,35 @@
#pragma pack (push, 1)
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryS3Data2Guid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_NODE 2
+#define MAX_CH 4
+#define MAX_DDR5_CH 2
+#define MAX_DIMM 2
+
+#define MAX_RANK_IN_CHANNEL (4)
+#define MAX_SDRAM_IN_DIMM (5)
+
+// Must match definitions in
+// Intel\OneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h
+#define HOB_MAX_SAGV_POINTS 4
+
+///
+/// Host reset states from MRC.
+///
+#define WARM_BOOT 2
+
+#define R_MC_CHNL_RANK_PRESENT 0x7C
+#define B_RANK0_PRS BIT0
+#define B_RANK1_PRS BIT1
+#define B_RANK2_PRS BIT4
+#define B_RANK3_PRS BIT5
+
+// @todo remove and use the MdePkg\Include\Pi\PiHob.h
#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__)
#ifndef __HOB__H__
typedef struct _EFI_HOB_GENERIC_HEADER {
@@ -40,6 +69,17 @@ typedef struct _EFI_HOB_GUID_TYPE {
#endif
#endif
+///
+/// Defines taken from MRC to avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
//
// MRC version description.
//
@@ -97,16 +137,231 @@ typedef enum {
} MRC_BOOT_MODE;
#endif //__MRC_BOOT_MODE__
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_LPDDR5
+#define MRC_DDR_TYPE_LPDDR5 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR5
+#define MRC_DDR_TYPE_DDR5 1
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 2
+#endif
+
+#define MAX_PROFILE_NUM 7 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported
+
+#ifndef MAX_RCOMP_TARGETS
+#define MAX_RCOMP_TARGETS 5
+#endif
+
+#ifndef MAX_ODT_ENTRIES
+#define MAX_ODT_ENTRIES 11
+#endif
+
+#ifndef MAX_COPY_DIMM_DFE_TAPS
+#define MAX_COPY_DIMM_DFE_TAPS 2
+#endif
+
+#define MAX_TRACE_REGION 5
+#define MAX_TRACE_CACHE_TYPE 2
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT32 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+ UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
+ UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group.
+ UINT8 Resv[2]; ///< Reserved.
+} MRC_CH_TIMING;
+
+typedef struct {
+ UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay
+} MRC_IP_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId; ///< Dram module manufacturer ID
+ UINT16 CkdMfgID; ///< Clock Driver (CKD) Manufacturer ID
+ UINT8 CkdDeviceRev; ///< Clock Driver (CKD) device revision
+ UINT16 DramMfgID; ///< Manufacturer ID code for DRAM chip on the module
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+ UINT16 Speed; ///< The maximum capable speed of the device, in MHz
+ UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation.
+ UINT8 Banks; ///< Number of banks the DIMM contains.
+ UINT8 BankGroups; ///< Number of bank groups the DIMM contains.
+ UINT8 DeviceDensity; ///< Device Density in Gb
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+//
+// Each DIMM Slot Mechanical present bit map
+//
+typedef struct {
+ UINT8 MrcSlotMap[MAX_NODE][MAX_CH];
+} MRC_SLOTMAP;
+
+typedef struct {
+ UINT64 BaseAddress; ///< Trace Base Address
+ UINT64 TotalSize; ///< Total Trace Region of Same Cache type
+ UINT8 CacheType; ///< Trace Cache Type
+ UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code
+ UINT8 Rsvd[2];
+} PSMI_MEM_INFO;
+
+/// This data structure contains per-SaGv timing values that are considered output by the MRC.
+typedef struct {
+ UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s
+ MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec
+ MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific
+ UINT16 MaxMemoryBandwidth; ///< Maximum theoretical bandwidth in GB/s supported by GV
+} HOB_SAGV_TIMING_OUT;
+
+/// This data structure contains SAGV config values that are considered output by the MRC.
+typedef struct {
+ UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled.
+ UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point.
+ HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS];
+} HOB_SAGV_INFO;
+
+typedef struct _PPR_RESULT_COLUMNS_HOB {
+ UINT8 PprRowRepairsSuccessful;
+ UINT8 Controller;
+ UINT8 Channel;
+ UINT8 Rank;
+ UINT8 BankGroup;
+ UINT8 Bank;
+ UINT32 Row;
+ UINT8 Device;
+} PPR_RESULT_COLUMNS_HOB;
+
/**
Memory Info Data Hob
+
+ <b>Revision 1:</b>
+ - Initial version. (from MTL)
+ <b>Revision 2:</b>
+ - Added MopPackages, MopDensity, MopRanks, MopVendor fields
+
**/
typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth; ///< Data width, in bits, of this memory device
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
+ UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed
+ BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise.
+ UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ UINT32 VddqVoltage[MAX_PROFILE_NUM];
+ UINT32 VppVoltage[MAX_PROFILE_NUM];
+ UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS];
+ UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES];
+ INT8 DimmDFE[MAX_PROFILE_NUM][MAX_DDR5_CH][MAX_DIMM][MAX_COPY_DIMM_DFE_TAPS];
+ CONTROLLER_INFO Controller[MAX_NODE];
+ UINT32 NumPopulatedChannels; ///< Total number of memory channels populated
+ HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC.
+ BOOLEAN IsIbeccEnabled;
+ UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels
+ UINT8 MopPackages; ///< Mop DRAM package population
+ UINT8 MopDensity; ///< Mop DRAM die density
+ UINT8 MopRanks; ///< Mop Number of ranks
+ UINT8 MopVendor; ///< Mop DRAM vendor ID
+ UINT8 PprRanInLastBoot; ///< Whether PPR ran in the prior boot
+ UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows
+ UINT16 PprRepairFails; ///< PPR: Counts of repair failure
+ UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status
+ UINT16 PprRepairsSuccessful; ///< PPR: Counts of repair successes
+ PPR_RESULT_COLUMNS_HOB PprErrorInfo; ///< PPR: Error location
+ UINT8 PprAvailableResources[MAX_NODE][MAX_CH][MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; ///< PPR available resources per device
} MEMORY_INFO_DATA_HOB;
/**
Memory Platform Data Hob
+
+ <b>Revision 1:</b>
+ - Initial version.
+ <b>Revision 2:</b>
+ - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
**/
typedef struct {
+ UINT8 Revision;
+ UINT8 Reserved[3];
+ UINT32 BootMode;
+ UINT32 TsegSize;
+ UINT32 TsegBase;
+ UINT32 PrmrrSize;
+ UINT64 PrmrrBase;
+ UINT32 GttBase;
+ UINT32 MmioSize;
+ UINT32 PciEBaseAddress;
+ PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];
+ PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION];
+ BOOLEAN MrcBasicMemoryTestPass;
} MEMORY_PLATFORM_DATA;
typedef struct {
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 16:07:00 +0000