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authorArthur Heymans <arthur@aheymans.xyz>2022-11-01 23:31:26 +0100
committerArthur Heymans <arthur@aheymans.xyz>2022-11-07 13:58:23 +0000
commit49af4f7f9197e559b2c7142129441679bb1d24a2 (patch)
treeb7c7db10ddf1f27f7f2e1febc2cb23ca48e183e0 /src/vendorcode
parent5d152122284880029c123fe2b7dfa20cd8b74632 (diff)
{cpu/nb}/amd/family16: Remove platform
This platform use the LEGACY_SMP_INIT which is to be deprecated after release 4.18. Change-Id: I589f30ccf81b6cf243ac7cbf8320a3f830649ad8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69117 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode')
-rw-r--r--src/vendorcode/amd/agesa/Kconfig14
-rw-r--r--src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c5
2 files changed, 1 insertions, 18 deletions
diff --git a/src/vendorcode/amd/agesa/Kconfig b/src/vendorcode/amd/agesa/Kconfig
index 4468cc3b34..4bc6a3d569 100644
--- a/src/vendorcode/amd/agesa/Kconfig
+++ b/src/vendorcode/amd/agesa/Kconfig
@@ -159,20 +159,6 @@ config CUSTOM_SPD_TRC
default 181
range 1 255
-if CPU_AMD_AGESA_FAMILY16_KB
-
-config CUSTOM_SPD_TRFC_LO
- int "[24]: Min Refresh Recovery Delay Time, LOWER tRFC"
- default 56
- range 1 255
-
-config CUSTOM_SPD_TRFC_HI
- int "[25]: Min Refresh Recovery Delay Time, UPPER tRFC"
- default 14
- range 0 255
-
-endif
-
config CUSTOM_SPD_TWTR
int "[26]: Min Internal Write to Read Command Delay, tWTR"
default 105
diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
index d3c8303711..08d7fcb5d0 100644
--- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
+++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/mp.c
@@ -489,10 +489,7 @@ MemPIsIdSupported (
return TRUE;
}
}
- if (CONFIG(FORCE_AM1_SOCKET_SUPPORT))
- return TRUE;
- else
- return FALSE;
+ return FALSE;
}
/* -----------------------------------------------------------------------------*/