diff options
| author | Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> | 2021-07-06 17:12:27 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-07 14:49:15 +0000 |
| commit | c6ed254835a731625cb2a7d0c7b91e98f518a3d6 (patch) | |
| tree | 822937b84b44b9d424fca43bfac579b5210ae921 /src/vendorcode/mediatek/mt8195/dramc | |
| parent | e53cbfdbf40332ce766ecd8490e97e986a057c45 (diff) | |
vc/mediatek/mt8195: Improve settings of duty calibration
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: Ic4aeaec947356001d073df72977899ca06b18bda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'src/vendorcode/mediatek/mt8195/dramc')
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c | 26 |
1 files changed, 17 insertions, 9 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c index cea83a06fe..16f16ff0e4 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_pi_calibration_api.c @@ -14804,18 +14804,26 @@ void DramcNewDutyCalibration(DRAMC_CTX_T *p) #endif #endif { + U8 u1ChannelIdx; + U8 u1backup_channel = vGetPHY2ChannelMapping(p); + #if SUPPORT_SAVE_TIME_FOR_CALIBRATION if(p->femmc_Ready==1) { - DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]); - DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]); - #if __LP5_COMBO__ - WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]); - #endif - #if APPLY_DQDQM_DUTY_CALIBRATION - DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM); - DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ); - #endif + for(u1ChannelIdx=CHANNEL_A; u1ChannelIdx<p->support_channel_num; u1ChannelIdx++){ + vSetPHY2ChannelMapping(p, u1ChannelIdx); + + DramcClockDutySetClkDelayCell(p, p->pSavetimeData->s1ClockDuty_clk_delay_cell[p->channel]); + DQSDutyScan_SetDqsDelayCell(p, p->pSavetimeData->s1DQSDuty_clk_delay_cell[p->channel]); + #if __LP5_COMBO__ + WCKDutyScan_SetWCKDelayCell(p, p->pSavetimeData->s1WCKDuty_clk_delay_cell[p->channel]); + #endif + #if APPLY_DQDQM_DUTY_CALIBRATION + DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQMDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQM); + DQDQMDutyScan_SetDQDQMDelayCell(p, p->channel, p->pSavetimeData->s1DQDuty_clk_delay_cell[p->channel], DutyScan_Calibration_K_DQ); + #endif + } + vSetPHY2ChannelMapping(p, u1backup_channel); vSetCalibrationResult(p, DRAM_CALIBRATION_DUTY_SCAN, DRAM_FAST_K); return; |