vc/mediatek/mt8195: Remove unused code and comments

Remove unused code and comment to align with the latest MTK memory
reference code which is from MTK internal dram driver code without
upstream.
version: Ib59134533ced8de09d23dd9f347c934d315166e2

TEST=boot to kernel

Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I95ab3cf8809ad22a341ceb7fd53a68e13fb0420d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58635
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 180 insertions, 223 deletions

diff --git a/src/vendorcode/mediatek/mt8195/dramc/emi.c b/src/vendorcode/mediatek/mt8195/dramc/emi.c
index 6649e82b97..5a1f09de50 100644
--- a/src/vendorcode/mediatek/mt8195/dramc/emi.c
+++ b/src/vendorcode/mediatek/mt8195/dramc/emi.c
@@ -39,12 +39,12 @@ static inline unsigned int mt_emi_sync_read(unsigned long long addr)
 static void emi_cen_config(void)  {
 
 #ifndef ONE_CH
-  #ifdef RANK_512MB  // => 2channel , dual rank , total=2G
+  #ifdef RANK_512MB
     mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xa053a154);
   #else
-    #ifdef RANK_1GB  //RANK_1G  => 2channel , dual rank , total=4G
+    #ifdef RANK_1GB
       mt_emi_sync_write(EMI_APB_BASE+0x00000000,0xf053f154);
-    #else  // RANK_2G => 2channel , dual rank , total=8G
+    #else
       #ifdef RANK_2GB
         mt_emi_sync_write(EMI_APB_BASE+0x00000000,0x00530154);
       #endif
@@ -58,58 +58,58 @@ static void emi_cen_config(void)  {
   #endif
 #endif
 
-  // overhead: 20190821 item1 - synced
-  mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33); //3733 (1:8) r4  - r1  overhead  // TBD - change to 4266
-  mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025); //3733 (1:8) r8  - r5  overhead  // TBD - change to 4266
-  mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027); //3733 (1:8) r12 - r9  overhead  // TBD - change to 4266
-  mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d); //3733 (1:8) r16 - r13 overhead  // TBD - change to 4266
-  mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33); //3200 (1:8) r4  - r1  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025); //3200 (1:8) r8  - r5  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027); //3200 (1:8) r12 - r9  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d); //3200 (1:8) r16 - r13 overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c); //2400 (1:8) r4  - r1  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21); //2400 (1:8) r8  - r5  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23); //2400 (1:8) r12 - r9  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228); //2400 (1:8) r16 - r13 overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28); //1866 (1:8) r4  - r1  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20); //1866 (1:8) r8  - r5  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24); //1866 (1:8) r12 - r9  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229); //1866 (1:8) r16 - r13 overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28); //1600 (1:8) r4  - r1  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20); //1600 (1:8) r8  - r5  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24); //1600 (1:8) r12 - r9  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229); //1600 (1:8) r16 - r13 overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28); //1200 (1:8) r4  - r1  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20); //1200 (1:8) r8  - r5  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24); //1200 (1:8) r12 - r9  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229); //1200 (1:8) r16 - r13 overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28); //800  (1:4) r12 - r9  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322); //800  (1:4) r4  - r1  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a); //800  (1:4) r16 - r13 overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f); //800  (1:4) r8  - r5  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28); //800  (1:4) r12 - r9  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322); //800  (1:4) r4  - r1  overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a); //800  (1:4) r16 - r13 overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f); //800  (1:4) r8  - r5  overhead
-
-  mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57); //3733 (1:8) r8  - r2  non-align overhead  // TBD - change to 4266
-  mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39); //3733 (1:8) r16 - r10 non-align overhead  // TBD - change to 4266
-  mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e); //3200 (1:8) r8  - r2  non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a); //3200 (1:8) r16 - r10 non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241); //2400 (1:8) r8  - r2  non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835); //2400 (1:8) r16 - r10 non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542); //1866 (1:8) r8  - r2  non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835); //1866 (1:8) r16 - r10 non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542); //1600 (1:8) r8  - r2  non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835); //1600 (1:8) r16 - r10 non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542); //1200 (1:8) r8  - r2  non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835); //1200 (1:8) r16 - r10 non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034); //800  (1:4) r8  - r2  non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39); //800  (1:4) r16 - r10 non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034); //800  (1:4) r8  - r2  non-align overhead
-  mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39); //800  (1:4) r16 - r10 non-align overhead
-
-  //
+
+  mt_emi_sync_write(EMI_APB_BASE+0x00000004,0x182e2d33);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000008,0x0f251025);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000000c,0x122a1027);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000010,0x1a31162d);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008b0,0x182e2d33);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008b4,0x0f251025);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000001c,0x122a1027);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000024,0x1a31162d);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000034,0x1024202c);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000006c,0x0b210c21);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000013c,0x0f250d23);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000640,0x152b1228);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000044,0x0c201a28);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000074,0x0d230a20);
+  mt_emi_sync_write(EMI_APB_BASE+0x000001e0,0x0e260d24);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000644,0x132d1229);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000004c,0x0c201a28);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000084,0x0d230a20);
+  mt_emi_sync_write(EMI_APB_BASE+0x000001e4,0x0e260d24);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000648,0x132d1229);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000054,0x0c201a28);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000008c,0x0d230a20);
+  mt_emi_sync_write(EMI_APB_BASE+0x000001e8,0x0e260d24);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000064c,0x132d1229);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000005c,0x0e290e28);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000094,0x091e1322);
+  mt_emi_sync_write(EMI_APB_BASE+0x000001c8,0x0f29112a);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000660,0x0c240a1f);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000064,0x0e290e28);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000009c,0x091e1322);
+  mt_emi_sync_write(EMI_APB_BASE+0x000001f4,0x0f29112a);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000664,0x0c240a1f);
+
+  mt_emi_sync_write(EMI_APB_BASE+0x00000030,0x37373a57);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000014,0x3f3f3c39);
+  mt_emi_sync_write(EMI_APB_BASE+0x000008b8,0x3836374e);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000002c,0x41413d3a);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000c4,0x33313241);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000668,0x3a3a3835);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000c8,0x34343542);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000066c,0x3b3b3835);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000cc,0x34343542);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000694,0x3b3b3835);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000e4,0x34343542);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000708,0x3b3b3835);
+  mt_emi_sync_write(EMI_APB_BASE+0x000000f4,0x37333034);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000070c,0x39393a39);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000012c,0x37333034);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000748,0x39393a39);
+
+
   mt_emi_sync_write(EMI_APB_BASE+0x00000018,0x3657587a);
   mt_emi_sync_write(EMI_APB_BASE+0x00000020,0x0000c042);
   mt_emi_sync_write(EMI_APB_BASE+0x00000028,0x08421000);
@@ -121,17 +121,17 @@ static void emi_cen_config(void)  {
   mt_emi_sync_write(EMI_APB_BASE+0x0000003c,0x00073210);
   mt_emi_sync_write(EMI_APB_BASE+0x00000040,0x00008802);
   mt_emi_sync_write(EMI_APB_BASE+0x00000048,0x00000000);
-  mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff); // reserved buffer to normal read/write :8/7
+  mt_emi_sync_write(EMI_APB_BASE+0x00000060,0x007812ff);
   mt_emi_sync_write(EMI_APB_BASE+0x00000068,0x00000000);
-  mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f);  //22:20=ultra_w=1
-  mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f);  //22:20=ultra_w=1
+  mt_emi_sync_write(EMI_APB_BASE+0x00000078,0x11120c1f);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000710,0x11120c1f);
   mt_emi_sync_write(EMI_APB_BASE+0x0000007c,0x00001123);
   mt_emi_sync_write(EMI_APB_BASE+0x00000718,0x00001123);
   mt_emi_sync_write(EMI_APB_BASE+0x000000d0,0xa8a8a8a8);
   mt_emi_sync_write(EMI_APB_BASE+0x000000d4,0x25252525);
   mt_emi_sync_write(EMI_APB_BASE+0x000000d8,0xa8a8a8a8);
   mt_emi_sync_write(EMI_APB_BASE+0x000000dc,0x25252525);
-  mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037); // initial starvation counter div2, [4]=1
+  mt_emi_sync_write(EMI_APB_BASE+0x000000e8,0x00060037);
   mt_emi_sync_write(EMI_APB_BASE+0x000000f0,0x384a0014);
   mt_emi_sync_write(EMI_APB_BASE+0x000000f8,0xa0000000);
   mt_emi_sync_write(EMI_APB_BASE+0x00000100,0x20107244);
@@ -146,38 +146,38 @@ static void emi_cen_config(void)  {
   mt_emi_sync_write(EMI_APB_BASE+0x00000144,0x00007108);
   mt_emi_sync_write(EMI_APB_BASE+0x00000150,0x090a0000);
   mt_emi_sync_write(EMI_APB_BASE+0x00000158,0xff0bff00);
-  mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001); //[27:20] enable monitor
+  mt_emi_sync_write(EMI_APB_BASE+0x00000400,0x00ff0001);
   mt_emi_sync_write(EMI_APB_BASE+0x0000071c,0x10000008);
   mt_emi_sync_write(EMI_APB_BASE+0x00000800,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x00000820,0x24240101);
   mt_emi_sync_write(EMI_APB_BASE+0x00000824,0x01012424);
   mt_emi_sync_write(EMI_APB_BASE+0x00000828,0x50500101);
   mt_emi_sync_write(EMI_APB_BASE+0x0000082c,0x01015050);
-  mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30); // [6] MD_HRT_URGENT_MASK, if 1 -> mask MD_HRT_URGENT,
+  mt_emi_sync_write(EMI_APB_BASE+0x00000830,0x0fc39a30);
   mt_emi_sync_write(EMI_APB_BASE+0x00000834,0x05050003);
   mt_emi_sync_write(EMI_APB_BASE+0x00000838,0x254dffff);
-  mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x0000083c,0x465a788c);
   mt_emi_sync_write(EMI_APB_BASE+0x00000840,0x000003e8);
   mt_emi_sync_write(EMI_APB_BASE+0x00000844,0x0000036b);
   mt_emi_sync_write(EMI_APB_BASE+0x00000848,0x00000290);
   mt_emi_sync_write(EMI_APB_BASE+0x0000084c,0x00000200);
   mt_emi_sync_write(EMI_APB_BASE+0x00000850,0x00000000);
   mt_emi_sync_write(EMI_APB_BASE+0x00000854,0x00000000);
-  mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff); //ignore rff threshold
-  mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785); //disable internal MD latency urgent mask
+  mt_emi_sync_write(EMI_APB_BASE+0x00000858,0x02531cff);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000085c,0x00002785);
   mt_emi_sync_write(EMI_APB_BASE+0x00000874,0x000001b5);
-  mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x00000878,0x003c0000);
   mt_emi_sync_write(EMI_APB_BASE+0x0000087c,0x0255250d);
   mt_emi_sync_write(EMI_APB_BASE+0x00000890,0xffff3c59);
   mt_emi_sync_write(EMI_APB_BASE+0x00000894,0xffff00ff);
   mt_emi_sync_write(EMI_APB_BASE+0x000008a0,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x000008a4,0x0000ffff);
   mt_emi_sync_write(EMI_APB_BASE+0x000008c0,0x0000014b);
-  mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x000008c4,0x002d0000);
   mt_emi_sync_write(EMI_APB_BASE+0x000008c8,0x00000185);
-  mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x000008cc,0x003c0000);
   mt_emi_sync_write(EMI_APB_BASE+0x000008d0,0x00000185);
-  mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000); //update
+  mt_emi_sync_write(EMI_APB_BASE+0x000008d4,0x003c0000);
   mt_emi_sync_write(EMI_APB_BASE+0x000008e0,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x000008e4,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x000008e8,0xffffffff);
@@ -209,7 +209,7 @@ static void emi_cen_config(void)  {
   mt_emi_sync_write(EMI_APB_BASE+0x00000c0c,0x64644b64);
   mt_emi_sync_write(EMI_APB_BASE+0x00000c40,0x01010101);
   mt_emi_sync_write(EMI_APB_BASE+0x00000c44,0x01010101);
-  mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025);	//ignore wff threshold
+  mt_emi_sync_write(EMI_APB_BASE+0x00000c4c,0x300ff025);
   mt_emi_sync_write(EMI_APB_BASE+0x00000c80,0x000003e8);
   mt_emi_sync_write(EMI_APB_BASE+0x00000c84,0x0000036b);
   mt_emi_sync_write(EMI_APB_BASE+0x00000c88,0x00000290);
@@ -223,47 +223,47 @@ static void emi_cen_config(void)  {
   mt_emi_sync_write(EMI_APB_BASE+0x00000cf8,0x01010101);
   mt_emi_sync_write(EMI_APB_BASE+0x00000cfc,0x01010101);
 
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009); //MDR shf0 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000); //MDR shf1 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000); //MDR shf0
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808); //MDR shf1
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028); //MDW shf0 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000); //MDW shf1 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000); //MDW shf0
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808); //MDW shf1
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080); //APR shf0 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000); //APR shf1 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008); //APR shf0/shf1
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800); //APW shf0 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000); //APW shf1 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000); //MMR shf0 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000); //MMR shf1 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000); //MMR shf1 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000); //MMR shf2 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800); //MMR shf2 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000); //MMR shf0
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030); //MMR shf1
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000); //MMW shf0 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000); //MMW shf1 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000); //MMW shf1 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000); //MMW shf2 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000); //MMW shf2 event selet
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000); //MMW shf0
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040); //MMW shf1
-  mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000); //MDHWR sh0 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000); //MDHWR sh1 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404); //MDHWWR sh
-  mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000); //MDHWW sh0 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000); //MDHWW sh1 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000); //GPUR sh0 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000); //GPUR sh1 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010); //GPUR
-  mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000); //GPUW sh0 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000); //GPUW sh1 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009); //ARBR sh0 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080); //ARBR sh1 event select
-  mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11); //ARB
-  mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7); //QOS control
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d04,0x00000009);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d0c,0x00000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d14,0x00730000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d18,0x00000808);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d1c,0x00000028);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d24,0x00000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d2c,0x00730000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d30,0x00000808);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d34,0x00000080);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d3c,0x00000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d44,0x30201008);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d48,0x00000800);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d50,0x00000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d58,0x00008000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d60,0x00020000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d64,0x00001000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d68,0x00010000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d6c,0x00000800);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d70,0x08080000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d74,0x00073030);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d78,0x00040000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d80,0x00100000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d84,0x00004000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d88,0x00080000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d8c,0x00002000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d90,0x08080000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d94,0x00074040);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000d98,0x00400000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000da0,0x00200000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000da8,0x10100404);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dac,0x01000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000db4,0x00800000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dbc,0x04000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dc4,0x02000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dcc,0x60602010);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dd0,0x10000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000dd8,0x08000000);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000de0,0x00000009);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000de8,0x04400080);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000df0,0x0f170f11);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000df4,0x0303f7f7);
   mt_emi_sync_write(EMI_APB_BASE+0x00000e04,0x00000166);
   mt_emi_sync_write(EMI_APB_BASE+0x00000e08,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x00000e0c,0xffffffff);
@@ -277,51 +277,50 @@ static void emi_cen_config(void)  {
   mt_emi_sync_write(EMI_APB_BASE+0x00000e38,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x00000e3c,0xffffffff);
 
-  // Added by Wei-Lun - START
-  // prtcl chker - golden setting
-  mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff); // cyc
-  mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85); // ctl
-  mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff); // msk
+
+  mt_emi_sync_write(EMI_APB_BASE+0x00000304,0xffffffff);
+  mt_emi_sync_write(EMI_APB_BASE+0x0000030c,0x001ffc85);
+  mt_emi_sync_write(EMI_APB_BASE+0x00000314,0xffffffff);
 
   mt_emi_sync_write(EMI_APB_BASE+0x0000034c,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x00000354,0x001ffc85);
-  mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff); // msk
+  mt_emi_sync_write(EMI_APB_BASE+0x0000035c,0xffffffff);
 
   mt_emi_sync_write(EMI_APB_BASE+0x00000394,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x0000039c,0x001ffc85);
-  mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff); // msk
+  mt_emi_sync_write(EMI_APB_BASE+0x000003a4,0xffffffff);
 
   mt_emi_sync_write(EMI_APB_BASE+0x000003d8,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x000003dc,0x001ffc85);
-  mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff); // msk
+  mt_emi_sync_write(EMI_APB_BASE+0x000003e0,0xffffffff);
 
   mt_emi_sync_write(EMI_APB_BASE+0x000003fc,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x0000040c,0x001ffc85);
-  mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff); // msk
+  mt_emi_sync_write(EMI_APB_BASE+0x00000414,0xffffffff);
 
   mt_emi_sync_write(EMI_APB_BASE+0x0000044c,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x00000454,0x001ffc85);
-  mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff); // msk
+  mt_emi_sync_write(EMI_APB_BASE+0x0000045c,0xffffffff);
 
   mt_emi_sync_write(EMI_APB_BASE+0x0000049c,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x000004a4,0x001ffc85);
-  mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff); // msk
+  mt_emi_sync_write(EMI_APB_BASE+0x000004ac,0xffffffff);
 
   mt_emi_sync_write(EMI_APB_BASE+0x0000050c,0xffffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x00000514,0x001ffc85);
-  mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff); // msk
+  mt_emi_sync_write(EMI_APB_BASE+0x0000051c,0xffffffff);
+
+
+  mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000);
 
-  //weilun for new feature
-  mt_emi_sync_write(EMI_APB_BASE+0x00000714,0x00000000); // dvfs level setting for chn_emi rw switching shf
 
-  // cen_emi timeout value
   mt_emi_sync_write(EMI_APB_BASE+0x00000628,0x60606060);
   mt_emi_sync_write(EMI_APB_BASE+0x0000062c,0x60606060);
 
-  // fine-grained qos
+
   mt_emi_sync_write(EMI_APB_BASE+0x00000050,0x00000000);
 
-  // ostd->bw
+
   mt_emi_sync_write(EMI_APB_BASE+0x0000061c,0x08ffbbff);
   mt_emi_sync_write(EMI_APB_BASE+0x00000624,0xffff5b3c);
   mt_emi_sync_write(EMI_APB_BASE+0x00000774,0xffff00ff);
@@ -330,16 +329,16 @@ static void emi_cen_config(void)  {
   mt_emi_sync_write(EMI_APB_BASE+0x0000078c,0x00ffffff);
   mt_emi_sync_write(EMI_APB_BASE+0x00000958,0x00000000);
 
-  // hash rule
+
   //mt_emi_sync_write(EMI_APB_BASE+0x000007a4,0xC0000000);
 }
 
 static void emi_chn_config(void)  {
 
-#ifdef RANK_512MB  // => 2channel , dual rank , total=2G
+#ifdef RANK_512MB
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400a051);
 #else
-  #ifdef RANK_1GB //RANK_1G  => 2channel , dual rank , total=4G
+  #ifdef RANK_1GB
     mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000000,0x0400f051);
   #else
     #ifdef RANK_2GB
@@ -350,26 +349,26 @@ static void emi_chn_config(void)  {
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000008,0x00ff6048);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000010,0x00000004);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000018,0x99f08c03);
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17); // [24:20] = 0x2 : bank throttling (default=0x01f00000)
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137); //RD_INORDER_THR[20:16]=2
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002); // [1] : MD_RD_AFT_WR_EN
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000710,0x9a508c17);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000048,0x00038137);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000050,0x38460002);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000058,0x00000000);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000090,0x000002ff);
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003111); //mw2
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000098,0x00003111);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000140,0x22607188);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000144,0x22607188);
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x3719595e); // chuan
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x2719595e); // chuan
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000148,0x3719595e);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000014c,0x2719595e);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000150,0x64f3ff79);
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3ff79); // update timeout setting: bit 12~15
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000154,0x64f3ff79);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000158,0x011b0868);
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0xa7414222); // Stop urgent read first when write command buffer remain < 7, [31] ultra_read_first, [30:28] wr_rsv_thr_l, [27:    24] wr_rsv_thr_h, 
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000015c,0xa7414222);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x0000016c,0x0000f801);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000170,0x40000000);
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c802f); // Rank-Aware arbitration
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e); // Rank-Aware arbitration
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e); // Rank-Aware arbitration
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000003fc,0x00000000); // Write M17_toggle_mask = 0
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0,0x000c802f);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b4,0xbd3f3f7e);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b8,0x7e003d7e);
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000003fc,0x00000000);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000080,0xaa0148ff);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000088,0xaa6168ff);
   mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x00000404,0xaa516cff);
@@ -385,10 +384,10 @@ static void emi_sw_setting(void)
 
 	enable_infra_emi_broadcast(1);
 
-	/* mpu irq settings. separate emi mpu and devmpu irq */
+
 	*((volatile unsigned int *) EMI_CONH) = *((volatile unsigned int *) EMI_CONH) | 0xC0;
 
-	/* for DVFS BW monitor */
+
 	*((volatile unsigned int *) EMI_BWCT0) = 0x05000305;
 	*((volatile unsigned int *) EMI_BWCT0_6TH) = 0x08FF0705;
 	*((volatile unsigned int *) EMI_BWCT0_3RD) = 0x0DFF0A05;
@@ -423,10 +422,10 @@ static void emi_sw_setting(void)
 	}
 #endif
 
-	/* align urgent monitor countrol to bus monitor */
+
 	*((volatile unsigned int *)0x10219858) |= 0x1 << 11;
 
-	/* EMI doeapp for DCM */
+
 	emi_dcm = 0;
 	emi_log("[EMI DOE] emi_dcm %d\n", emi_dcm);
 	if (emi_dcm == 1) {
@@ -446,9 +445,9 @@ void emi_init(void)
 	//unsigned int domain = 0;
 	//char *str;
 
-	mt_emi_sync_write(EMI_BASE+0x000007a4, 0xC0000000);     // config emi for 2+2CH
+	mt_emi_sync_write(EMI_BASE+0x000007a4, 0xC0000000);
 #ifdef SUB_EMI_BASE
-	mt_emi_sync_write(SUB_EMI_BASE+0x000007a4, 0xD0000000); // config sub emi for 2+2CH
+	mt_emi_sync_write(SUB_EMI_BASE+0x000007a4, 0xD0000000);
 #endif
 
 	enable_infra_emi_broadcast(1);
@@ -465,27 +464,26 @@ void emi_init2(void)
 
   enable_infra_emi_broadcast(1);
 
-  mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001);   // [0] EMI enable
-  mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400);        //[10] EMI enable
+  mt_emi_sync_write_or(CHN0_EMI_BASE+0x00000010, 0x00000001);
+  mt_emi_sync_write_or(EMI_BASE+0x00000060, 0x00000400);
 
   #ifdef REAL_CHIP_EMI_GOLDEN_SETTING
 
 
-  mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010); // [4] Disable emi_mpu_reg interrupt
+  mt_emi_sync_write_or(EMI_MPU_BASE+0x00000000,0x00000010);
+
 
-  // Clear rank_arb_en
-  emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x000001b0); // read ch0
+  emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x000001b0);
   emi_temp_data = emi_temp_data & ~(0x1);
-  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); // broadcast to all channel
-  // auto-config rank_arb_en according to dual_rank_en setting
-  // assume all channel with same configuration
-  emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x00000000); // read ch0
+  mt_emi_sync_write(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data);
+
+  emi_temp_data = mt_emi_sync_read(EMI_CHANNEL_APB_BASE+0x00000000);
   emi_temp_data = emi_temp_data & 0x1;
-  mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data); // broadcast to all channel
+  mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x000001b0, emi_temp_data);
 
   enable_infra_emi_broadcast(0);
 
-  // ----- from dcm_setting.c -----
+
   mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x100, 0xFFFFFFFF);
   mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x104, 0xFFFFFFFF);
   mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x108, 0xFFFFFFFF);
@@ -546,13 +544,13 @@ void emi_init2(void)
 
   mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x038, 0xA00001FF);
 
-  mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000); // enable infra_local_cg
+  mt_emi_sync_write_or(INFRACFG_AO_BASE+0x00000078, 0x08000000);
 
   #ifdef EMI_MP_SETTING
-  // Enable rdata_prty_gen & wdata_prty_chk
-  mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000);  // enable cen_emi parity (w)
 
-  // emi bus parity workaround
+  mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00400000);
+
+
   emi_temp_data = mt_emi_sync_read(0x40000000);
   mt_emi_sync_write(0x40000000, emi_temp_data);
   emi_temp_data = mt_emi_sync_read(0x40000100);
@@ -562,61 +560,20 @@ void emi_init2(void)
   emi_temp_data = mt_emi_sync_read(0x40000300);
   mt_emi_sync_write(0x40000300, emi_temp_data);
 
-  mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000004); // enable chn_emi parity
-
-  //// Enable APMCU Early CKE
-  //// set reg_chn_en
-  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
-  //emi_temp_data = (emi_temp_data >>  6) & (0x1<<2);
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
-  //// set reg_chn_pos
-  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
-  //emi_temp_data = (emi_temp_data <<  2) & (0x3<<4);
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
-  //// set reg_chn_loc
-  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
-  //emi_temp_data = (emi_temp_data >>  4) & (0x1<<6);
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
-  //// set reg_dual_rank_en
-  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
-  //emi_temp_data = (emi_temp_data >> 10) & (0x1<<7);
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
-  //// set reg_cas_size[1:0]
-  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
-  //emi_temp_data = (emi_temp_data >>  9) & (0x3<<9);
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
-  //// set reg_cas_size[2]
-  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
-  //emi_temp_data = (emi_temp_data << 11) & (0x1<<11);
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
-  //// set reg_cas_size[3]
-  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000000);
-  //emi_temp_data = (emi_temp_data >> 14) & (0x1<<12);
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
-  //// set reg_remap_shift
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x00006000);
-  //// set reg_rank_dec0
-  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x00000038);
-  //emi_temp_data = (emi_temp_data <<  2) & (0x1f<<18);
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, emi_temp_data);
-  //// set reg_rank_cke_ext and reg_enable
-  //mt_emi_sync_write_or(EMI_APB_BASE+0x000007f4, 0x11000001);
-  //// set to mcusys
-  //emi_temp_data = mt_emi_sync_read(EMI_APB_BASE+0x000007f4);
-  //mt_emi_sync_write(MCUSYS_PAR_WRAP_BASE+0x0000a490, emi_temp_data);
-
-  /*TINFO="program hash rule"*/
+  mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000004);
+
+
   mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021);
-  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); // set disph_chg_en = 0x1
+  mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021);
+
 
-  /*TINFO="read emi_reg_pd then write apmcu config reg"*/
   emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050);
   emi_temp_data = emi_temp_data & 0xf;
   mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data);
 
-  /*TINFO="Enable EMI wdata bus encode function"*/
-  mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000); // enable cen_emi wdata bus encode          // *EMI_CONN |= (0x1 << 21);
-  mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000010); // enable chn_emi wdata bus encode  // *CHN0_EMI_CHN_EMI_DFTC |= (0x1 <<4);
+
+  mt_emi_sync_write_or(EMI_APB_BASE+0x00000068,0x00200000);
+  mt_emi_sync_write_or(EMI_CHANNEL_APB_BASE+0x00000050,0x00000010);
   #else
   // MP_dsim_v02 test (from v01) - all fr
   //mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x028, 0x003F0000);
@@ -626,27 +583,27 @@ void emi_init2(void)
   #endif
 
 
-  /*TINFO="program hash rule"*/
+
   if (channel_num_auxadc == CHANNEL_FOURTH)
   	{
       mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000021);
-      mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021); // set disph_chg_en = 0x1
+      mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000021);
   	}
-  else /* CHANNEL_DUAL */
+  else
   	{
       mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x00000007);
-      mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007); // set disph_chg_en = 0x1
+      mt_emi_sync_write(INFRACFG_AO_MEM_BASE+0x00000050, 0x80000007);
   	}
 
 
-  /*TINFO="read emi_reg_pd then write apmcu config reg"*/
+
   emi_temp_data = mt_emi_sync_read(INFRACFG_AO_MEM_BASE+0x050);
   emi_temp_data = emi_temp_data & 0xf;
 
   enable_infra_emi_broadcast(1);
   mt_emi_sync_write_or(EMI_BASE+0x07A4, emi_temp_data);
 
-  mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040); // disable EBG
+  mt_emi_sync_write(CHN0_EMI_BASE+0x0020, 0x00000040);
   enable_infra_emi_broadcast(0);
 
   emi_sw_setting();
@@ -809,7 +766,7 @@ unsigned int get_cen_emi_cona(void)
 	return mt_emi_sync_read(EMI_CONA);
 }
 
-/* assume all chn emi setting are the same */
+
 unsigned int get_chn_emi_cona(void)
 {
 	unsigned int ch0_emi_cona;
@@ -897,7 +854,7 @@ void phy_addr_to_dram_addr(dram_addr_t *dram_addr, unsigned long long phy_addr)
 static unsigned int cen_emi_conh_backup = 0;
 static unsigned int chn_emi_cona_backup = 0;
 
-/* return the start address of rank1 */
+
 unsigned int set_emi_before_rank1_mem_test(void)
 {
 	cen_emi_conh_backup = mt_emi_sync_read(EMI_CONH);
@@ -905,13 +862,13 @@ unsigned int set_emi_before_rank1_mem_test(void)
 
 	enable_infra_emi_broadcast(1);
 	if (get_rank_nr_by_emi() == 2) {
-		/* set the rank size to 1GB for 2 channels */
+
 		mt_emi_sync_write(EMI_CONH,
 			(cen_emi_conh_backup & 0x0000ffff) | 0x22220000);
 		set_chn_emi_cona(
 			(chn_emi_cona_backup & 0xff00ffff) | 0x00220000);
 	} else {
-		/* set the rank size to 1GB for 1 channel */
+
 		mt_emi_sync_write(EMI_CONH,
 			(cen_emi_conh_backup & 0x0000ffff) | 0x44440000);
 		set_chn_emi_cona(
@@ -1053,7 +1010,7 @@ void record_emi_snst(void)
 	last_emi_info_ptr->snst_last = mt_emi_sync_read(EMI_SNST);
 	emi_log("[EMI] SNST: 0x%x\n", last_emi_info_ptr->snst_last);
 
-	/* clear EMI_SNST and set target master to M5 */
+
 	mt_emi_sync_write(EMI_SNST, 0x85000000);
 #endif
 }