diff options
| author | Kulkarni, Srinivas <srinivas.kulkarni@intel.com> | 2023-12-16 10:00:57 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2023-12-17 20:14:45 +0000 |
| commit | 520ca9a51876177b3b99c01a4b2206cc3edbd3a4 (patch) | |
| tree | 26d73ec555f91c878c337dc8a0f0200176e9b952 /src/vendorcode/intel | |
| parent | 224098dffd8f1f59b2345e1bd27691f7d5e94f31 (diff) | |
vc/intel/raptorlake: Update header files from 4301_01 to 4435_00
Update header files for FSP for Raptor Lake platform to version 4435_00,
previous version being 4301_01.
FSPM:
1. Options changed for Ppr Enable
2. Add 'Ppr Run Once' and 'Post Package Repair' UPD's
FSPS:
1. Add 'CpuPcieRpTestForceLtrOverride' UPD
MemInfoHob:
1. Structure updated
BUG=b:315234533
Kit: https://www.intel.com/content/www/us/en/secure/design/confidential/
software-kits/kit-details.html?kitId=793230
Cq-Depend: chrome-internal:6786881, chrome-internal:6787635
Cq-Depend: chrome-internal:6719974, chromium:5125983
Change-Id: I65b8a4b6c72f7ae3fff1ee6d073311d154cd6b69
Signed-off-by: Kulkarni, Srinivas <srinivas.kulkarni@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Diffstat (limited to 'src/vendorcode/intel')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h | 14 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h | 2 | ||||
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/raptorlake/MemInfoHob.h | 2 |
3 files changed, 14 insertions, 4 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h index 7a4706aca7..83241efc87 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspmUpd.h @@ -3754,8 +3754,8 @@ typedef struct { UINT32 SerialIoUartDebugCtsPinMux; /** Offset 0x0AA8 - Ppr Enable Type - Enable Soft or Hard PPR <b>0:Disable</b>, 2:Hard PPR - 0:Disable, 2:Hard PPR + Enable Soft or Hard PPR 0:Disable, 1:Soft PPR, <b>2:Hard PPR</b>, 3:No Repair + 0:Disable, 1:Soft PPR, 2:Hard PPR, 3:No Repair **/ UINT8 PprEnable; @@ -3795,8 +3795,16 @@ typedef struct { UINT8 CpuPcieRpSlotImplemented[4]; /** Offset 0x0AB6 + Enable PPR Run Once 0:Disable, <b>1:Enable<b> + 0:Disable, 1:Enable +**/ + UINT8 PprRunOnce; + +/** Offset 0x0AB7 - Post Package Repair + Enables/Disable Post Package Repair + $EN_DIS **/ - UINT8 Rsvd28[2]; + UINT8 PPR; /** Offset 0x0AB8 - IbeccErrInjAddress Address to match against for ECC error injection diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h index aef704ea7d..1fe07e4589 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/FspsUpd.h @@ -4296,7 +4296,7 @@ typedef struct { /** Offset 0x104C **/ - UINT8 Rsvd39[4]; + UINT8 CpuPcieRpTestForceLtrOverride[4]; /** Offset 0x1050 - MemoryBuffer MemoryBuffer address diff --git a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/MemInfoHob.h index 378a559646..57ea2ca3a9 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/raptorlake/MemInfoHob.h +++ b/src/vendorcode/intel/fsp/fsp2_0/raptorlake/MemInfoHob.h @@ -281,6 +281,8 @@ typedef struct { BOOLEAN MemorySpeedReducedWrongDimmSlot; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to wrong DIMM population BOOLEAN MemorySpeedReducedMixedConfig; ///< Can be used by OEM BIOS to display a warning on the screen that DDR speed was reduced due to mixed DIMM config BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. + UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows. + UINT16 PprRepairFails; ///< PPR: Counts of repair failure. } MEMORY_INFO_DATA_HOB; /** |