diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2022-07-05 22:31:29 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-20 12:42:11 +0000 |
| commit | 3d5fd72c0f1673e539db918497cdb5e0403bb874 (patch) | |
| tree | e13a0ea4f9310d454d32423f1403ba4d065ebc49 /src/vendorcode/intel | |
| parent | 3108ba5a070559cd1a682edb448bd2ccf474833a (diff) | |
soc/intel/xeon_sp: Put SRAT util macros into Xeon-SP ACPI header
Macros MAX_ACPI_MEMORY_AFFINITY_COUNT and MAX_SRAT_MEM_ENTRIES_PER_IMC
are ACPI table specific, and could be used across Xeon-SP SoCs.
This patch moves their definition from FSP header to Xeon-SP layer
ACPI header.
TEST=intel/archercity CRB
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Change-Id: I6c3a84b04a452bc8d4217947a7d12f050c94b56b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80629
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel')
3 files changed, 0 insertions, 12 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index eef8cc6c24..573b5c3f0a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -55,10 +55,6 @@ are permitted provided that the following conditions are met: #define MAX_SAD_RULES 24 #define MAX_DRAM_CLUSTERS 1 #define MAX_IMC_PER_SOCKET 2 -#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 -#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \ - MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \ - ) #define MEM_TYPE_RESERVED (1 << 8) #define MEM_ADDR_64MB_SHIFT_BITS 26 diff --git a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h index 0cf1f863b6..040414b213 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/hob_memmap.h @@ -40,11 +40,7 @@ are permitted provided that the following conditions are met: } #define MAX_IMC_PER_SOCKET MAX_IMC -#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 #define MAX_SMB_INSTANCE 2 -#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \ - MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \ - ) #define AMT_MAX_NODE ((MAX_AMT)*(MAX_SOCKET)) // Max abstract memory target for all sockets #endif // _HOB_MEMMAP_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h index 3440ab7461..c35b2f6285 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h @@ -41,10 +41,6 @@ are permitted provided that the following conditions are met: #define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) #define MAX_IMC_PER_SOCKET 2 -#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 -#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \ - MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \ - ) #define MEM_TYPE_RESERVED (1 << 8) #define MEM_ADDR_64MB_SHIFT_BITS 26 |