diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-02-07 17:00:41 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-02-10 23:58:29 +0000 |
| commit | 3dd7d84c7c2e98eba8e5a6580a481ef7a8e5f89b (patch) | |
| tree | 95b59e0be01332262a59aba24ad7b780f4bc1b28 /src/vendorcode/intel/fsp1_0/rangeley | |
| parent | b924f405701f7d4182f1f1af7164e69acf87d4fd (diff) | |
mainboard/google/meowth: Enable ECT again
Previously ECT was disabled in commit 22401, on D0 stepping system and
FSP version 7.x.20.52, disabling ECT will cause memory training failure
and the system is stuck at post code 00D5h.
BUG=b.72473063
TEST=Apply patch and build coreboot image, flash into meowth P0 system
with D0 stepping silicon installed, system can pass memory training and
boot up into OS.
Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/vendorcode/intel/fsp1_0/rangeley')
0 files changed, 0 insertions, 0 deletions