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authorJonathan Zhang <jonzhang@fb.com>2022-08-08 15:38:54 -0700
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-11-08 22:55:20 +0000
commitfe17a7d4d420763ef387e84256eaed0373c25725 (patch)
treeae5069dfc9631a2300b3437dfed03bee45310d35 /src/vendorcode/intel/fsp/fsp2_0
parenta2503fa2e9c1c69495c29c4dfb00e7413952523d (diff)
soc/intel/xeon_sp: accomodate xeon_sp FSPX_CONFIG definitions
Intel FSPs of XEON server platforms define FSPX_CONFIG instead of FSP_X_CONFIG, which is expected by coreboot. Re-define in the common code. Update coreboot code to use FSP_X_CONFIG consistently. Tested=On OCP Delta Lake, boot up OS successfully. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
index 0de0fa1ee8..066c2aef24 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FspmUpd.h
@@ -553,7 +553,7 @@ typedef struct {
/** Offset 0x01E0
**/
UINT8 ReservedMemoryInitUpd[16];
-} FSP_M_CONFIG;
+} FSPM_CONFIG;
/** Fsp M UPD Configuration
**/