summaryrefslogtreecommitdiff
path: root/src/vendorcode/intel/fsp/fsp2_0
diff options
context:
space:
mode:
authorKilari Raasi <kilari.raasi@intel.com>2023-01-30 16:02:34 +0530
committerSubrata Banik <subratabanik@google.com>2023-02-17 07:52:31 +0000
commiteac71c0bcf49477c56c252d4c3ead0d6006e1ecf (patch)
treef118d75d763a7a18791dedeaf974d0ec92598531 /src/vendorcode/intel/fsp/fsp2_0
parent718a7ae62dc59ece08f8b7849e691873e9216258 (diff)
vc/intel/fsp/mtl: Update header files from 2473_86 to 2523_80
Update header files for FSP for Meteor Lake platform to version 2523_80, previous version being 2473_86. FSPM: 1. Rename DMI UPDs 2. Address offset changes FSPS: 1. Address offset changes BUG=b:266499304 Change-Id: Ib4b8478bc3558ef863b6b52e685f981a5891e4a9 Signed-off-by: Kilari Raasi <kilari.raasi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72591 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0')
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h1022
-rw-r--r--src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h575
2 files changed, 809 insertions, 788 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
index f4892793d4..d62ae2d70a 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -547,15 +547,19 @@ typedef struct {
/** Offset 0x019C - Reserved
**/
- UINT8 Reserved7[3];
+ UINT8 Reserved7[6];
-/** Offset 0x019F - Memory Reference Clock
+/** Offset 0x01A2 - Memory Reference Clock
100MHz, 133MHz.
0:133MHz, 1:100MHz
**/
UINT8 RefClk;
-/** Offset 0x01A0 - Memory Vdd Voltage
+/** Offset 0x01A3 - Reserved
+**/
+ UINT8 Reserved8;
+
+/** Offset 0x01A4 - Memory Vdd Voltage
DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM
chips) in millivolts. <b>0=Platform Default (no override)</b>, 1200=1.2V, 1350=1.35V etc.
0:Default, 1200:1.20 Volts, 1250:1.25 Volts, 1300:1.30 Volts, 1350:1.35 Volts, 1400:1.40
@@ -563,76 +567,76 @@ typedef struct {
**/
UINT16 VddVoltage;
-/** Offset 0x01A2 - Reserved
+/** Offset 0x01A6 - Reserved
**/
- UINT8 Reserved8[4];
+ UINT8 Reserved9[4];
-/** Offset 0x01A6 - Memory Ratio
+/** Offset 0x01AA - Memory Ratio
Automatic or the frequency will equal ratio times reference clock. Set to Auto to
recalculate memory timings listed below.
0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15
**/
UINT16 Ratio;
-/** Offset 0x01A8 - tCL
+/** Offset 0x01AC - tCL
CAS Latency, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
== 1 (Custom Profile).
**/
UINT8 tCL;
-/** Offset 0x01A9 - tCWL
+/** Offset 0x01AD - tCWL
Min CAS Write Latency Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
== 1 (Custom Profile).
**/
UINT8 tCWL;
-/** Offset 0x01AA - tFAW
+/** Offset 0x01AE - tFAW
Min Four Activate Window Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
== 1 (Custom Profile).
**/
UINT16 tFAW;
-/** Offset 0x01AC - tRAS
+/** Offset 0x01B0 - tRAS
RAS Active Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
== 1 (Custom Profile).
**/
UINT16 tRAS;
-/** Offset 0x01AE - tRCD/tRP
+/** Offset 0x01B2 - tRCD/tRP
RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 255. Only used
if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
**/
UINT8 tRCDtRP;
-/** Offset 0x01AF - Reserved
+/** Offset 0x01B3 - Reserved
**/
- UINT8 Reserved9;
+ UINT8 Reserved10;
-/** Offset 0x01B0 - tREFI
+/** Offset 0x01B4 - tREFI
Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
== 1 (Custom Profile).
**/
UINT16 tREFI;
-/** Offset 0x01B2 - tRFC
+/** Offset 0x01B6 - tRFC
Min Refresh Recovery Delay Time, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected
== 1 (Custom Profile).
**/
UINT16 tRFC;
-/** Offset 0x01B4 - tRRD
+/** Offset 0x01B8 - tRRD
Min Row Active to Row Active Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
== 1 (Custom Profile).
**/
UINT8 tRRD;
-/** Offset 0x01B5 - tRTP
+/** Offset 0x01B9 - tRTP
Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 255. Only used
if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
**/
UINT8 tRTP;
-/** Offset 0x01B6 - tWR
+/** Offset 0x01BA - tWR
Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18,
20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile).
0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30,
@@ -640,74 +644,74 @@ typedef struct {
**/
UINT8 tWR;
-/** Offset 0x01B7 - tWTR
+/** Offset 0x01BB - tWTR
Min Internal Write to Read Command Delay Time, 0: AUTO, max: 255. Only used if FspmUpd->FspmConfig.SpdProfileSelected
== 1 (Custom Profile).
**/
UINT8 tWTR;
-/** Offset 0x01B8 - Reserved
+/** Offset 0x01BC - Reserved
**/
- UINT8 Reserved10[11];
+ UINT8 Reserved11[11];
-/** Offset 0x01C3 - NMode
+/** Offset 0x01C7 - NMode
System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N
**/
UINT8 NModeSupport;
-/** Offset 0x01C4 - Enable Intel HD Audio (Azalia)
+/** Offset 0x01C8 - Enable Intel HD Audio (Azalia)
0: Disable, 1: Enable (Default) Azalia controller
$EN_DIS
**/
UINT8 PchHdaEnable;
-/** Offset 0x01C5 - Enable PCH ISH Controller
+/** Offset 0x01C9 - Enable PCH ISH Controller
0: Disable, 1: Enable (Default) ISH Controller
$EN_DIS
**/
UINT8 PchIshEnable;
-/** Offset 0x01C6 - SAGV Gear Ratio
+/** Offset 0x01CA - SAGV Gear Ratio
Gear Selection for SAGV points. 0 - Auto, 2-Gear 2, 4-Gear 4
**/
UINT8 SaGvGear[4];
-/** Offset 0x01CA - SAGV Frequency
+/** Offset 0x01CE - SAGV Frequency
SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300.
**/
UINT16 SaGvFreq[4];
-/** Offset 0x01D2 - SAGV Disabled Gear Ratio
+/** Offset 0x01D6 - SAGV Disabled Gear Ratio
Gear Selection for SAGV Disabled. 0 - Auto, 2-Gear 2, 2-Gear 4
**/
UINT8 GearRatio;
-/** Offset 0x01D3 - Reserved
+/** Offset 0x01D7 - Reserved
**/
- UINT8 Reserved11[69];
+ UINT8 Reserved12[69];
-/** Offset 0x0218 - MMIO size adjustment for AUTO mode
+/** Offset 0x021C - MMIO size adjustment for AUTO mode
Positive number means increasing MMIO size, Negative value means decreasing MMIO
size: 0 (Default)=no change to AUTO mode MMIO size
**/
UINT16 MmioSizeAdjustment;
-/** Offset 0x021A - Selection of the primary display device
+/** Offset 0x021E - Selection of the primary display device
0=iGFX, 3(Default)=AUTO, 4=Hybrid Graphics
0:iGFX, 3:AUTO, 4:Hybrid Graphics
**/
UINT8 PrimaryDisplay;
-/** Offset 0x021B - Reserved
+/** Offset 0x021F - Reserved
**/
- UINT8 Reserved12;
+ UINT8 Reserved13;
-/** Offset 0x021C - Temporary MMIO address for GMADR
+/** Offset 0x0220 - Temporary MMIO address for GMADR
Obsolete field now and it has been extended to 64 bit address, used LMemBar
**/
UINT32 GmAdr;
-/** Offset 0x0220 - Temporary MMIO address for GTTMMADR
+/** Offset 0x0224 - Temporary MMIO address for GTTMMADR
The reference code will use this as Temporary MMIO address space to access GTTMMADR
Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr
to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO
@@ -715,179 +719,179 @@ typedef struct {
**/
UINT32 GttMmAdr;
-/** Offset 0x0224 - Enable/Disable MRC TXT dependency
+/** Offset 0x0228 - Enable/Disable MRC TXT dependency
When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default):
MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization
$EN_DIS
**/
UINT8 TxtImplemented;
-/** Offset 0x0225 - Enable/Disable SA OcSupport
+/** Offset 0x0229 - Enable/Disable SA OcSupport
Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport
$EN_DIS
**/
UINT8 SaOcSupport;
-/** Offset 0x0226 - GT slice Voltage Mode
+/** Offset 0x022A - GT slice Voltage Mode
0(Default): Adaptive, 1: Override
0: Adaptive, 1: Override
**/
UINT8 GtVoltageMode;
-/** Offset 0x0227 - Maximum GTs turbo ratio override
+/** Offset 0x022B - Maximum GTs turbo ratio override
0(Default)=Minimal/Auto, 60=Maximum
**/
UINT8 GtMaxOcRatio;
-/** Offset 0x0228 - The voltage offset applied to GT slice
+/** Offset 0x022C - The voltage offset applied to GT slice
0(Default)=Minimal, 1000=Maximum
**/
UINT16 GtVoltageOffset;
-/** Offset 0x022A - The GT slice voltage override which is applied to the entire range of GT frequencies
+/** Offset 0x022E - The GT slice voltage override which is applied to the entire range of GT frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtVoltageOverride;
-/** Offset 0x022C - adaptive voltage applied during turbo frequencies
+/** Offset 0x0230 - adaptive voltage applied during turbo frequencies
0(Default)=Minimal, 2000=Maximum
**/
UINT16 GtExtraTurboVoltage;
-/** Offset 0x022E - voltage offset applied to the SA
+/** Offset 0x0232 - voltage offset applied to the SA
0(Default)=Minimal, 1000=Maximum
**/
UINT16 SaVoltageOffset;
-/** Offset 0x0230 - PCIe root port Function number for Hybrid Graphics dGPU
+/** Offset 0x0234 - PCIe root port Function number for Hybrid Graphics dGPU
Root port Index number to indicate which PCIe root port has dGPU
**/
UINT8 RootPortIndex;
-/** Offset 0x0231 - Realtime Memory Timing
+/** Offset 0x0235 - Realtime Memory Timing
0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform
realtime memory timing changes after MRC_DONE.
0: Disabled, 1: Enabled
**/
UINT8 RealtimeMemoryTiming;
-/** Offset 0x0232 - Reserved
+/** Offset 0x0236 - Reserved
**/
- UINT8 Reserved13;
+ UINT8 Reserved14;
-/** Offset 0x0233 - Enable/Disable SA IPU
+/** Offset 0x0237 - Enable/Disable SA IPU
Enable(Default): Enable SA IPU, Disable: Disable SA IPU
$EN_DIS
**/
UINT8 SaIpuEnable;
-/** Offset 0x0234 - IMGU CLKOUT Configuration
+/** Offset 0x0238 - IMGU CLKOUT Configuration
The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>.
$EN_DIS
**/
UINT8 ImguClkOutEn[6];
-/** Offset 0x023A - Program GPIOs for LFP on DDI port-A device
+/** Offset 0x023E - Program GPIOs for LFP on DDI port-A device
0=Disabled,1(Default)=eDP, 2=MIPI DSI
0:Disabled, 1:eDP, 2:MIPI DSI
**/
UINT8 DdiPortAConfig;
-/** Offset 0x023B - Program GPIOs for LFP on DDI port-B device
+/** Offset 0x023F - Program GPIOs for LFP on DDI port-B device
0(Default)=Disabled,1=eDP, 2=MIPI DSI
0:Disabled, 1:eDP, 2:MIPI DSI
**/
UINT8 DdiPortBConfig;
-/** Offset 0x023C - Enable or disable HPD of DDI port A
+/** Offset 0x0240 - Enable or disable HPD of DDI port A
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortAHpd;
-/** Offset 0x023D - Enable or disable HPD of DDI port B
+/** Offset 0x0241 - Enable or disable HPD of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBHpd;
-/** Offset 0x023E - Enable or disable HPD of DDI port C
+/** Offset 0x0242 - Enable or disable HPD of DDI port C
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortCHpd;
-/** Offset 0x023F - Enable or disable HPD of DDI port 1
+/** Offset 0x0243 - Enable or disable HPD of DDI port 1
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPort1Hpd;
-/** Offset 0x0240 - Enable or disable HPD of DDI port 2
+/** Offset 0x0244 - Enable or disable HPD of DDI port 2
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort2Hpd;
-/** Offset 0x0241 - Enable or disable HPD of DDI port 3
+/** Offset 0x0245 - Enable or disable HPD of DDI port 3
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort3Hpd;
-/** Offset 0x0242 - Enable or disable HPD of DDI port 4
+/** Offset 0x0246 - Enable or disable HPD of DDI port 4
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort4Hpd;
-/** Offset 0x0243 - Enable or disable DDC of DDI port A
+/** Offset 0x0247 - Enable or disable DDC of DDI port A
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortADdc;
-/** Offset 0x0244 - Enable or disable DDC of DDI port B
+/** Offset 0x0248 - Enable or disable DDC of DDI port B
0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 DdiPortBDdc;
-/** Offset 0x0245 - Enable or disable DDC of DDI port C
+/** Offset 0x0249 - Enable or disable DDC of DDI port C
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPortCDdc;
-/** Offset 0x0246 - Enable DDC setting of DDI Port 1
+/** Offset 0x024A - Enable DDC setting of DDI Port 1
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort1Ddc;
-/** Offset 0x0247 - Enable DDC setting of DDI Port 2
+/** Offset 0x024B - Enable DDC setting of DDI Port 2
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort2Ddc;
-/** Offset 0x0248 - Enable DDC setting of DDI Port 3
+/** Offset 0x024C - Enable DDC setting of DDI Port 3
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort3Ddc;
-/** Offset 0x0249 - Enable DDC setting of DDI Port 4
+/** Offset 0x024D - Enable DDC setting of DDI Port 4
0(Default)=Disable, 1=Enable
$EN_DIS
**/
UINT8 DdiPort4Ddc;
-/** Offset 0x024A - Reserved
+/** Offset 0x024E - Reserved
**/
- UINT8 Reserved14[14];
+ UINT8 Reserved15[18];
-/** Offset 0x0258 - Per-core HT Disable
+/** Offset 0x0260 - Per-core HT Disable
Defines the per-core HT disable mask where: 1 - Disable selected logical core HT,
0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value
of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have
@@ -895,11 +899,11 @@ typedef struct {
**/
UINT16 PerCoreHtDisable;
-/** Offset 0x025A - Reserved
+/** Offset 0x0262 - Reserved
**/
- UINT8 Reserved15[6];
+ UINT8 Reserved16[6];
-/** Offset 0x0260 - Thermal Velocity Boost Ratio clipping
+/** Offset 0x0268 - Thermal Velocity Boost Ratio clipping
0: Disabled, 1(Default): Enabled. This service controls Core frequency reduction
caused by high package temperatures for processors that implement the Intel Thermal
Velocity Boost (TVB) feature
@@ -907,32 +911,32 @@ typedef struct {
**/
UINT8 TvbRatioClipping;
-/** Offset 0x0261 - Thermal Velocity Boost voltage optimization
+/** Offset 0x0269 - Thermal Velocity Boost voltage optimization
0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations
for processors that implement the Intel Thermal Velocity Boost (TVB) feature.
$EN_DIS
**/
UINT8 TvbVoltageOptimization;
-/** Offset 0x0262 - Reserved
+/** Offset 0x026A - Reserved
**/
- UINT8 Reserved16[47];
+ UINT8 Reserved17[45];
-/** Offset 0x0291 - DMI Max Link Speed
+/** Offset 0x0297 - DMI Max Link Speed
Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1
Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed
0:Auto, 1:Gen1, 2:Gen2, 3:Gen3
**/
UINT8 DmiMaxLinkSpeed;
-/** Offset 0x0292 - DMI Equalization Phase 2
+/** Offset 0x0298 - PCH DMI Equalization Phase 2
DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default):
AUTO - Use the current default method
0:Disable phase2, 1:Enable phase2, 2:Auto
**/
- UINT8 DmiGen3EqPh2Enable;
+ UINT8 PchDmiGen3EqPh2Enable;
-/** Offset 0x0293 - DMI Gen3 Equalization Phase3
+/** Offset 0x0299 - PCH DMI Gen3 Equalization Phase3
DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method,
HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software
Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static
@@ -940,58 +944,62 @@ typedef struct {
Phase1), Disabled(0x4): Bypass Equalization Phase 3
0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3
**/
- UINT8 DmiGen3EqPh3Method;
+ UINT8 PchDmiGen3EqPh3Method;
-/** Offset 0x0294 - Enable/Disable DMI GEN3 Static EQ Phase1 programming
+/** Offset 0x029A - Enable/Disable DMI GEN3 Static EQ Phase1 programming
Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static
Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 DmiGen3ProgramStaticEq;
-/** Offset 0x0295 - DMI Gen3 Root port preset values per lane
+/** Offset 0x029B - PCH DMI Gen3 Root port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 4 is default for each lane
**/
- UINT8 DmiGen3RootPortPreset[8];
+ UINT8 PchDmiGen3RootPortPreset[8];
-/** Offset 0x029D - DMI Gen3 End port preset values per lane
+/** Offset 0x02A3 - PCH DMI Gen3 End port preset values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane
**/
- UINT8 DmiGen3EndPointPreset[8];
+ UINT8 PchDmiGen3EndPointPreset[8];
-/** Offset 0x02A5 - DMI Gen3 End port Hint values per lane
+/** Offset 0x02AB - PCH DMI Gen3 End port Hint values per lane
Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane
**/
- UINT8 DmiGen3EndPointHint[8];
+ UINT8 PchDmiGen3EndPointHint[8];
-/** Offset 0x02AD - DMI ASPM Configuration:{Combo
+/** Offset 0x02B3 - DMI ASPM Configuration:{Combo
Set ASPM Configuration
0:Disabled, 1:L0s, 2:L1, 3:L1L0s
**/
UINT8 DmiAspm;
-/** Offset 0x02AE - Enable/Disable DMI GEN3 Hardware Eq
+/** Offset 0x02B4 - Reserved
+**/
+ UINT8 Reserved18;
+
+/** Offset 0x02B5 - Enable/Disable DMI GEN3 Hardware Eq
Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0): Disable Hardware Eq, Enabled(0x1)(Default):
Enable EQ Phase1 Static Presets Programming
$EN_DIS
**/
UINT8 DmiHweq;
-/** Offset 0x02AF - Enable/Disable DMI GEN3 Phase 23 Bypass
+/** Offset 0x02B6 - Enable/Disable DMI GEN3 Phase 23 Bypass
DMIGEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1):
Enable Phase 23 Bypass
$EN_DIS
**/
UINT8 Gen3EqPhase23Bypass;
-/** Offset 0x02B0 - Enable/Disable DMI GEN3 Phase 3 Bypass
+/** Offset 0x02B7 - Enable/Disable DMI GEN3 Phase 3 Bypass
DMIGEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1):
Enable Phase 3 Bypass
$EN_DIS
**/
UINT8 Gen3EqPhase3Bypass;
-/** Offset 0x02B1 - Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable
+/** Offset 0x02B8 - Enable/Disable DMI Gen3 EQ Local Transmitter Coefficient Override Enable
Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0): Disable Local
Transmitter Coefficient Override, Enabled(0x1)(Default): Enable Local Transmitter
Coefficient Override
@@ -999,7 +1007,7 @@ typedef struct {
**/
UINT8 Gen3LtcoEnable;
-/** Offset 0x02B2 - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable
+/** Offset 0x02B9 - Enable/Disable DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable
Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default):
Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote
Transmitter Coefficient/Preset Override
@@ -1007,271 +1015,271 @@ typedef struct {
**/
UINT8 Gen3RtcoRtpoEnable;
-/** Offset 0x02B3 - DMI Gen3 Transmitter Pre-Cursor Coefficient
+/** Offset 0x02BA - DMI Gen3 Transmitter Pre-Cursor Coefficient
Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10,
2 is default for each lane
**/
UINT8 DmiGen3Ltcpre[8];
-/** Offset 0x02BB - DMI Gen3 Transmitter Post-Cursor Coefficient
+/** Offset 0x02C2 - DMI Gen3 Transmitter Post-Cursor Coefficient
Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default
for each lane
**/
UINT8 DmiGen3Ltcpo[8];
-/** Offset 0x02C3 - Reserved
+/** Offset 0x02CA - Reserved
**/
- UINT8 Reserved17[16];
+ UINT8 Reserved19[34];
-/** Offset 0x02D3 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
+/** Offset 0x02EC - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable
Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable,
Manual(0x1): Enable DmiGen3DsPresetEnable
$EN_DIS
**/
UINT8 DmiGen3DsPresetEnable;
-/** Offset 0x02D4 - DMI Gen3 Root port preset Rx values per lane
+/** Offset 0x02ED - DMI Gen3 Root port preset Rx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default
for each lane
**/
UINT8 DmiGen3DsPortRxPreset[8];
-/** Offset 0x02DC - DMI Gen3 Root port preset Tx values per lane
+/** Offset 0x02F5 - DMI Gen3 Root port preset Tx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
for each lane
**/
UINT8 DmiGen3DsPortTxPreset[8];
-/** Offset 0x02E4 - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable
+/** Offset 0x02FD - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable
Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable,
Manual(0x1): Enable DmiGen3UsPresetEnable
$EN_DIS
**/
UINT8 DmiGen3UsPresetEnable;
-/** Offset 0x02E5 - DMI Gen3 Root port preset Rx values per lane
+/** Offset 0x02FE - DMI Gen3 Root port preset Rx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default
for each lane
**/
UINT8 DmiGen3UsPortRxPreset[8];
-/** Offset 0x02ED - DMI Gen3 Root port preset Tx values per lane
+/** Offset 0x0306 - DMI Gen3 Root port preset Tx values per lane
Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default
for each lane
**/
UINT8 DmiGen3UsPortTxPreset[8];
-/** Offset 0x02F5 - Reserved
+/** Offset 0x030E - Reserved
**/
- UINT8 Reserved18[54];
+ UINT8 Reserved20[54];
-/** Offset 0x032B - DMI ASPM L1 exit Latency
+/** Offset 0x0344 - DMI ASPM L1 exit Latency
Range: 0-7, 4 is default L1 exit Latency
**/
UINT8 DmiAspmL1ExitLatency;
-/** Offset 0x032C - Reserved
+/** Offset 0x0345 - Reserved
**/
- UINT8 Reserved19[40];
+ UINT8 Reserved21[63];
-/** Offset 0x0354 - BIST on Reset
+/** Offset 0x0384 - BIST on Reset
Enable/Disable BIST (Built-In Self Test) on reset. <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 BistOnReset;
-/** Offset 0x0355 - Skip Stop PBET Timer Enable/Disable
+/** Offset 0x0385 - Skip Stop PBET Timer Enable/Disable
Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 SkipStopPbet;
-/** Offset 0x0356 - Over clocking support
+/** Offset 0x0386 - Over clocking support
Over clocking support; <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 OcSupport;
-/** Offset 0x0357 - Over clocking Lock
+/** Offset 0x0387 - Over clocking Lock
Lock Overclocking. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 OcLock;
-/** Offset 0x0358 - Maximum Core Turbo Ratio Override
+/** Offset 0x0388 - Maximum Core Turbo Ratio Override
Maximum core turbo ratio override allows to increase CPU core frequency beyond the
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 if CoreRatioExtensionMode
is disabled. 0-120 if CoreRatioExtensionMode is enabled.
**/
UINT8 CoreMaxOcRatio;
-/** Offset 0x0359 - Core voltage mode
+/** Offset 0x0389 - Core voltage mode
Core voltage mode; <b>0: Adaptive</b>; 1: Override.
$EN_DIS
**/
UINT8 CoreVoltageMode;
-/** Offset 0x035A - Maximum clr turbo ratio override
+/** Offset 0x038A - Maximum clr turbo ratio override
Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the
fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85
**/
UINT8 RingMaxOcRatio;
-/** Offset 0x035B - Hyper Threading Enable/Disable
+/** Offset 0x038B - Hyper Threading Enable/Disable
Enable or Disable Hyper-Threading Technology. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 HyperThreading;
-/** Offset 0x035C - Enable or Disable CPU Ratio Override
+/** Offset 0x038C - Enable or Disable CPU Ratio Override
Enable/Disable CPU Flex Ratio Programming; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 CpuRatioOverride;
-/** Offset 0x035D - CPU ratio value
+/** Offset 0x038D - CPU ratio value
This value must be between Max Efficiency Ratio (LFM) and Maximum non-turbo ratio
set by Hardware (HFM). Valid Range 0 to 63.
**/
UINT8 CpuRatio;
-/** Offset 0x035E - Reserved
+/** Offset 0x038E - Reserved
**/
- UINT8 Reserved20;
+ UINT8 Reserved22;
-/** Offset 0x035F - Number of active big cores
+/** Offset 0x038F - Number of active big cores
Number of P-cores to enable in each processor package. Note: Number of P-Cores and
E-Cores are looked at together. When both are {0,0
0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores
**/
UINT8 ActiveCoreCount;
-/** Offset 0x0360 - Processor Early Power On Configuration FCLK setting
+/** Offset 0x0390 - Processor Early Power On Configuration FCLK setting
FCLK frequency can take values of 400MHz, 800MHz and 1GHz. <b>0: 800 MHz (ULT/ULX)</b>.
<b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved
0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved
**/
UINT8 FClkFrequency;
-/** Offset 0x0361 - Enable or Disable VMX
+/** Offset 0x0391 - Enable or Disable VMX
Enable or Disable VMX, When enabled, a VMM can utilize the additional hardware capabilities
provided by Vanderpool Technology. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 VmxEnable;
-/** Offset 0x0362 - AVX2 Ratio Offset
+/** Offset 0x0392 - AVX2 Ratio Offset
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
**/
UINT8 Avx2RatioOffset;
-/** Offset 0x0363 - AVX3 Ratio Offset
+/** Offset 0x0393 - AVX3 Ratio Offset
0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio
vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B.
**/
UINT8 Avx3RatioOffset;
-/** Offset 0x0364 - BCLK Adaptive Voltage Enable
+/** Offset 0x0394 - BCLK Adaptive Voltage Enable
When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0:
Disable;<b> 1: Enable
$EN_DIS
**/
UINT8 BclkAdaptiveVoltage;
-/** Offset 0x0365 - Reserved
+/** Offset 0x0395 - Reserved
**/
- UINT8 Reserved21;
+ UINT8 Reserved23;
-/** Offset 0x0366 - core voltage override
+/** Offset 0x0396 - core voltage override
The core voltage override which is applied to the entire range of cpu core frequencies.
Valid Range 0 to 2000
**/
UINT16 CoreVoltageOverride;
-/** Offset 0x0368 - Core Turbo voltage Adaptive
+/** Offset 0x0398 - Core Turbo voltage Adaptive
Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode.
Valid Range 0 to 2000
**/
UINT16 CoreVoltageAdaptive;
-/** Offset 0x036A - Core Turbo voltage Offset
+/** Offset 0x039A - Core Turbo voltage Offset
The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000
**/
UINT16 CoreVoltageOffset;
-/** Offset 0x036C - Core PLL voltage offset
+/** Offset 0x039C - Core PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 CorePllVoltageOffset;
-/** Offset 0x036D - Ring Downbin
+/** Offset 0x039D - Ring Downbin
Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always
lower than the core ratio.0: Disable; <b>1: Enable.</b>
$EN_DIS
**/
UINT8 RingDownBin;
-/** Offset 0x036E - Ring voltage mode
+/** Offset 0x039E - Ring voltage mode
Ring voltage mode; <b>0: Adaptive</b>; 1: Override.
$EN_DIS
**/
UINT8 RingVoltageMode;
-/** Offset 0x036F - TjMax Offset
+/** Offset 0x039F - TjMax Offset
TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support
TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63
**/
UINT8 TjMaxOffset;
-/** Offset 0x0370 - Ring voltage override
+/** Offset 0x03A0 - Ring voltage override
The ring voltage override which is applied to the entire range of cpu ring frequencies.
Valid Range 0 to 2000
**/
UINT16 RingVoltageOverride;
-/** Offset 0x0372 - Ring Turbo voltage Adaptive
+/** Offset 0x03A2 - Ring Turbo voltage Adaptive
Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode.
Valid Range 0 to 2000
**/
UINT16 RingVoltageAdaptive;
-/** Offset 0x0374 - Ring Turbo voltage Offset
+/** Offset 0x03A4 - Ring Turbo voltage Offset
The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000
**/
UINT16 RingVoltageOffset;
-/** Offset 0x0376 - Enable or Disable TME
+/** Offset 0x03A6 - Enable or Disable TME
Configure Total Memory Encryption (TME) to protect DRAM data from physical attacks.
<b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 TmeEnable;
-/** Offset 0x0377 - Enable CPU CrashLog
+/** Offset 0x03A7 - Enable CPU CrashLog
Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 CpuCrashLogEnable;
-/** Offset 0x0378 - CPU Run Control
+/** Offset 0x03A8 - CPU Run Control
Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2:
No Change</b>
0:Disabled, 1:Enabled, 2:No Change
**/
UINT8 DebugInterfaceEnable;
-/** Offset 0x0379 - CPU Run Control Lock
+/** Offset 0x03A9 - CPU Run Control Lock
Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 DebugInterfaceLockEnable;
-/** Offset 0x037A - Reserved
+/** Offset 0x03AA - Reserved
**/
- UINT8 Reserved22[67];
+ UINT8 Reserved24[67];
-/** Offset 0x03BD - Core VF Point Offset Mode
+/** Offset 0x03ED - Core VF Point Offset Mode
Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes.
In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode,
setting a selected VF point; <b>0: Legacy</b>; 1: Selection.
@@ -1279,54 +1287,54 @@ typedef struct {
**/
UINT8 CoreVfPointOffsetMode;
-/** Offset 0x03BE - Core VF Point Offset
+/** Offset 0x03EE - Core VF Point Offset
Array used to specifies the Core Voltage Offset applied to the each selected VF
Point. This voltage is specified in millivolts.
**/
UINT16 CoreVfPointOffset[15];
-/** Offset 0x03DC - Core VF Point Offset Prefix
+/** Offset 0x040C - Core VF Point Offset Prefix
Sets the CoreVfPointOffset value as positive or negative for corresponding core
VF Point; <b>0: Positive </b>; 1: Negative.
0:Positive, 1:Negative
**/
UINT8 CoreVfPointOffsetPrefix[15];
-/** Offset 0x03EB - Core VF Point Ratio
+/** Offset 0x041B - Core VF Point Ratio
Array for the each selected Core VF Point to display the ration.
**/
UINT8 CoreVfPointRatio[15];
-/** Offset 0x03FA - Core VF Point Count
+/** Offset 0x042A - Core VF Point Count
Number of supported Core Voltage & Frequency Point Offset
**/
UINT8 CoreVfPointCount;
-/** Offset 0x03FB - Reserved
+/** Offset 0x042B - Reserved
**/
- UINT8 Reserved23[25];
+ UINT8 Reserved25[25];
-/** Offset 0x0414 - Per Core Max Ratio override
+/** Offset 0x0444 - Per Core Max Ratio override
Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new
favored core ratio to each Core. <b>0: Disable</b>, 1: enable
$EN_DIS
**/
UINT8 PerCoreRatioOverride;
-/** Offset 0x0415 - Reserved
+/** Offset 0x0445 - Reserved
**/
- UINT8 Reserved24[41];
+ UINT8 Reserved26[41];
-/** Offset 0x043E - Per Core Current Max Ratio
+/** Offset 0x046E - Per Core Current Max Ratio
Array for the Per Core Max Ratio
**/
UINT8 PerCoreRatio[8];
-/** Offset 0x0446 - Reserved
+/** Offset 0x0476 - Reserved
**/
- UINT8 Reserved25[69];
+ UINT8 Reserved27[69];
-/** Offset 0x048B - Pvd Ratio Threshold for SOC/CPU die
+/** Offset 0x04BB - Pvd Ratio Threshold for SOC/CPU die
Array of Pvd Ratio Threshold for SOC/CPU die is the threshold value for input ratio
(P0 to Pn) to select the multiplier so that the output is within the DCO frequency
range. As per the die selected, this threshold is applied to SA and MC/CMI PLL
@@ -1335,76 +1343,76 @@ typedef struct {
**/
UINT8 PvdRatioThreshold[2];
-/** Offset 0x048D - Reserved
+/** Offset 0x04BD - Reserved
**/
- UINT8 Reserved26[70];
+ UINT8 Reserved28[68];
-/** Offset 0x04D3 - BCLK Frequency Source
+/** Offset 0x0501 - BCLK Frequency Source
Clock source of BCLK OC frequency, <b>0:CPU BCLK</b>, 1:PCH BCLK, 2:External CLK
0:CPU BCLK, 1:PCH BCLK, 2:External CLK
**/
UINT8 BclkSource;
-/** Offset 0x04D4 - GPIO Override
+/** Offset 0x0502 - GPIO Override
Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings
before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO
configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for use
**/
UINT8 GpioOverride;
-/** Offset 0x04D5 - Reserved
+/** Offset 0x0503 - Reserved
**/
- UINT8 Reserved27[7];
+ UINT8 Reserved29[9];
-/** Offset 0x04DC - CPU BCLK OC Frequency
+/** Offset 0x050C - CPU BCLK OC Frequency
CPU BCLK OC Frequency in KHz units. 98000000Hz = 98MHz <b>0 - Auto</b>. Range is
40Mhz-1000Mhz.
**/
UINT32 CpuBclkOcFrequency;
-/** Offset 0x04E0 - Reserved
+/** Offset 0x0510 - Reserved
**/
- UINT8 Reserved28[4];
+ UINT8 Reserved30[4];
-/** Offset 0x04E4 - Enable CPU CrashLog GPRs dump
+/** Offset 0x0514 - Enable CPU CrashLog GPRs dump
Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only
disable Smm GPRs dump
0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled
**/
UINT8 CrashLogGprs;
-/** Offset 0x04E5 - Reserved
+/** Offset 0x0515 - Reserved
**/
- UINT8 Reserved29[269];
+ UINT8 Reserved31[269];
-/** Offset 0x05F2 - Thermal Design Current enable/disable
+/** Offset 0x0622 - Thermal Design Current enable/disable
Thermal Design Current enable/disable; <b>0: Disable</b>; 1: Enable. [0] for IA,
[1] for GT, [2] for SA, [3] through [5] are Reserved.
**/
UINT8 TdcEnable[6];
-/** Offset 0x05F8 - Thermal Design Current time window
+/** Offset 0x0628 - Thermal Design Current time window
TDC Time Window, value of IA either in milliseconds or seconds, value of GT/SA is
in milliseconds. 1ms is default. Range of IA from 1ms to 448s, Range of GT/SA is
1ms to 10ms, except for 9ms. 9ms has no valid encoding in the MSR definition.
**/
UINT32 TdcTimeWindow[6];
-/** Offset 0x0610 - Reserved
+/** Offset 0x0640 - Reserved
**/
- UINT8 Reserved30[208];
+ UINT8 Reserved32[216];
-/** Offset 0x06E0 - BiosGuard
+/** Offset 0x0718 - BiosGuard
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
$EN_DIS
**/
UINT8 BiosGuard;
-/** Offset 0x06E1
+/** Offset 0x0719
**/
UINT8 BiosGuardToolsInterface;
-/** Offset 0x06E2 - Txt
+/** Offset 0x071A - Txt
Enables utilization of additional hardware capabilities provided by Intel (R) Trusted
Execution Technology. Changes require a full power cycle to take effect. <b>0:
Disable</b>, 1: Enable
@@ -1412,1254 +1420,1258 @@ typedef struct {
**/
UINT8 Txt;
-/** Offset 0x06E3 - Reserved
+/** Offset 0x071B - Reserved
**/
- UINT8 Reserved31;
+ UINT8 Reserved33;
-/** Offset 0x06E4 - PrmrrSize
+/** Offset 0x071C - PrmrrSize
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
**/
UINT32 PrmrrSize;
-/** Offset 0x06E8 - SinitMemorySize
+/** Offset 0x0720 - SinitMemorySize
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
**/
UINT32 SinitMemorySize;
-/** Offset 0x06EC - Reserved
+/** Offset 0x0724 - Reserved
**/
- UINT8 Reserved32[4];
+ UINT8 Reserved34[4];
-/** Offset 0x06F0 - TxtDprMemoryBase
+/** Offset 0x0728 - TxtDprMemoryBase
Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable
**/
UINT64 TxtDprMemoryBase;
-/** Offset 0x06F8 - TxtHeapMemorySize
+/** Offset 0x0730 - TxtHeapMemorySize
Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable
**/
UINT32 TxtHeapMemorySize;
-/** Offset 0x06FC - TxtDprMemorySize
+/** Offset 0x0734 - TxtDprMemorySize
Reserve DPR memory size (0-255) MB. 0: Disable, define default value of TxtDprMemorySize
, 1: enable
**/
UINT32 TxtDprMemorySize;
-/** Offset 0x0700 - BiosAcmBase
+/** Offset 0x0738 - BiosAcmBase
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
**/
UINT32 BiosAcmBase;
-/** Offset 0x0704 - BiosAcmSize
+/** Offset 0x073C - BiosAcmSize
Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable
**/
UINT32 BiosAcmSize;
-/** Offset 0x0708 - ApStartupBase
+/** Offset 0x0740 - ApStartupBase
Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable
**/
UINT32 ApStartupBase;
-/** Offset 0x070C - TgaSize
+/** Offset 0x0744 - TgaSize
Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable
**/
UINT32 TgaSize;
-/** Offset 0x0710 - TxtLcpPdBase
+/** Offset 0x0748 - TxtLcpPdBase
Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable
**/
UINT64 TxtLcpPdBase;
-/** Offset 0x0718 - TxtLcpPdSize
+/** Offset 0x0750 - TxtLcpPdSize
Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable
**/
UINT64 TxtLcpPdSize;
-/** Offset 0x0720 - IsTPMPresence
+/** Offset 0x0758 - IsTPMPresence
IsTPMPresence default values
**/
UINT8 IsTPMPresence;
-/** Offset 0x0721 - Reserved
+/** Offset 0x0759 - Reserved
**/
- UINT8 Reserved33[32];
+ UINT8 Reserved35[32];
-/** Offset 0x0741 - Enable PCH HSIO PCIE Rx Set Ctle
+/** Offset 0x0779 - Enable PCH HSIO PCIE Rx Set Ctle
Enable PCH PCIe Gen 3 Set CTLE Value.
**/
UINT8 PchPcieHsioRxSetCtleEnable[28];
-/** Offset 0x075D - PCH HSIO PCIE Rx Set Ctle Value
+/** Offset 0x0795 - PCH HSIO PCIE Rx Set Ctle Value
PCH PCIe Gen 3 Set CTLE Value.
**/
UINT8 PchPcieHsioRxSetCtle[28];
-/** Offset 0x0779 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
+/** Offset 0x07B1 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28];
-/** Offset 0x0795 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x07CD - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen1DownscaleAmp[28];
-/** Offset 0x07B1 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
+/** Offset 0x07E9 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28];
-/** Offset 0x07CD - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0805 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen2DownscaleAmp[28];
-/** Offset 0x07E9 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
+/** Offset 0x0821 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28];
-/** Offset 0x0805 - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
+/** Offset 0x083D - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value
PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchPcieHsioTxGen3DownscaleAmp[28];
-/** Offset 0x0821 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0859 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen1DeEmphEnable[28];
-/** Offset 0x083D - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
+/** Offset 0x0875 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value
PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen1DeEmph[28];
-/** Offset 0x0859 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
+/** Offset 0x0891 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28];
-/** Offset 0x0875 - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
+/** Offset 0x08AD - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value
PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen2DeEmph3p5[28];
-/** Offset 0x0891 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
+/** Offset 0x08C9 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28];
-/** Offset 0x08AD - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
+/** Offset 0x08E5 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value
PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting.
**/
UINT8 PchPcieHsioTxGen2DeEmph6p0[28];
-/** Offset 0x08C9 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x0901 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen1EqBoostMagEnable[8];
-/** Offset 0x08D1 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x0909 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen1EqBoostMag[8];
-/** Offset 0x08D9 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x0911 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen2EqBoostMagEnable[8];
-/** Offset 0x08E1 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x0919 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen2EqBoostMag[8];
-/** Offset 0x08E9 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
+/** Offset 0x0921 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioRxGen3EqBoostMagEnable[8];
-/** Offset 0x08F1 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
+/** Offset 0x0929 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value
PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value.
**/
UINT8 PchSataHsioRxGen3EqBoostMag[8];
-/** Offset 0x08F9 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x0931 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8];
-/** Offset 0x0901 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0939 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen1DownscaleAmp[8];
-/** Offset 0x0909 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x0941 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8];
-/** Offset 0x0911 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0949 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen2DownscaleAmp[8];
-/** Offset 0x0919 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+/** Offset 0x0951 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8];
-/** Offset 0x0921 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
+/** Offset 0x0959 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value
PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value.
**/
UINT8 PchSataHsioTxGen3DownscaleAmp[8];
-/** Offset 0x0929 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0961 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen1DeEmphEnable[8];
-/** Offset 0x0931 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x0969 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen1DeEmph[8];
-/** Offset 0x0939 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0971 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen2DeEmphEnable[8];
-/** Offset 0x0941 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x0979 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen2DeEmph[8];
-/** Offset 0x0949 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+/** Offset 0x0981 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
0: Disable; 1: Enable.
**/
UINT8 PchSataHsioTxGen3DeEmphEnable[8];
-/** Offset 0x0951 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
+/** Offset 0x0989 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting
PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting.
**/
UINT8 PchSataHsioTxGen3DeEmph[8];
-/** Offset 0x0959 - PCH LPC Enhance the port 8xh decoding
+/** Offset 0x0991 - PCH LPC Enhance the port 8xh decoding
Original LPC only decodes one byte of port 80h.
$EN_DIS
**/
UINT8 PchLpcEnhancePort8xhDecoding;
-/** Offset 0x095A - PCH Port80 Route
+/** Offset 0x0992 - PCH Port80 Route
Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.
$EN_DIS
**/
UINT8 PchPort80Route;
-/** Offset 0x095B - Enable SMBus ARP support
+/** Offset 0x0993 - Enable SMBus ARP support
Enable SMBus ARP support.
$EN_DIS
**/
UINT8 SmbusArpEnable;
-/** Offset 0x095C - Number of RsvdSmbusAddressTable.
+/** Offset 0x0994 - Number of RsvdSmbusAddressTable.
The number of elements in the RsvdSmbusAddressTable.
**/
UINT8 PchNumRsvdSmbusAddresses;
-/** Offset 0x095D - Reserved
+/** Offset 0x0995 - Reserved
**/
- UINT8 Reserved34;
+ UINT8 Reserved36;
-/** Offset 0x095E - SMBUS Base Address
+/** Offset 0x0996 - SMBUS Base Address
SMBUS Base Address (IO space).
**/
UINT16 PchSmbusIoBase;
-/** Offset 0x0960 - Enable SMBus Alert Pin
+/** Offset 0x0998 - Enable SMBus Alert Pin
Enable SMBus Alert Pin.
$EN_DIS
**/
UINT8 PchSmbAlertEnable;
-/** Offset 0x0961 - Usage type for ClkSrc
+/** Offset 0x0999 - Usage type for ClkSrc
0-23: PCH rootport, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used
**/
UINT8 PcieClkSrcUsage[18];
-/** Offset 0x0973 - Reserved
+/** Offset 0x09AB - Reserved
**/
- UINT8 Reserved35[14];
+ UINT8 Reserved37[14];
-/** Offset 0x0981 - ClkReq-to-ClkSrc mapping
+/** Offset 0x09B9 - ClkReq-to-ClkSrc mapping
Number of ClkReq signal assigned to ClkSrc
**/
UINT8 PcieClkSrcClkReq[18];
-/** Offset 0x0993 - Reserved
+/** Offset 0x09CB - Reserved
**/
- UINT8 Reserved36[57];
+ UINT8 Reserved38[57];
-/** Offset 0x09CC - Enable SOC/IOE PCIE RP Mask
+/** Offset 0x0A04 - Enable SOC/IOE PCIE RP Mask
Enable/disable SOC/IOE PCIE Root Ports. 0: disable, 1: enable. One bit for each
port, bit0 for port1, bit1 for port2, and so on.
**/
UINT16 PcieRpEnableMask;
-/** Offset 0x09CE - VC Type
+/** Offset 0x0A06 - VC Type
Virtual Channel Type Select: 0: VC0, 1: VC1.
0: VC0, 1: VC1
**/
UINT8 PchHdaVcType;
-/** Offset 0x09CF - Universal Audio Architecture compliance for DSP enabled system
+/** Offset 0x0A07 - Universal Audio Architecture compliance for DSP enabled system
0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox
driver or SST driver supported).
$EN_DIS
**/
UINT8 PchHdaDspUaaCompliance;
-/** Offset 0x09D0 - Enable HD Audio Link
+/** Offset 0x0A08 - Enable HD Audio Link
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
$EN_DIS
**/
UINT8 PchHdaAudioLinkHdaEnable;
-/** Offset 0x09D1 - Enable HDA SDI lanes
+/** Offset 0x0A09 - Enable HDA SDI lanes
Enable/disable HDA SDI lanes.
**/
UINT8 PchHdaSdiEnable[2];
-/** Offset 0x09D3 - HDA Power/Clock Gating (PGD/CGD)
+/** Offset 0x0A0B - HDA Power/Clock Gating (PGD/CGD)
Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1:
FORCE_ENABLE, 2: FORCE_DISABLE.
0: POR, 1: Force Enable, 2: Force Disable
**/
UINT8 PchHdaTestPowerClockGating;
-/** Offset 0x09D4 - Enable HD Audio DMIC_N Link
+/** Offset 0x0A0C - Enable HD Audio DMIC_N Link
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
**/
UINT8 PchHdaAudioLinkDmicEnable[2];
-/** Offset 0x09D6 - Reserved
+/** Offset 0x0A0E - Reserved
**/
- UINT8 Reserved37[2];
+ UINT8 Reserved39[2];
-/** Offset 0x09D8 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
+/** Offset 0x0A10 - DMIC<N> ClkA Pin Muxing (N - DMIC number)
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_*
**/
UINT32 PchHdaAudioLinkDmicClkAPinMux[2];
-/** Offset 0x09E0 - DMIC<N> ClkB Pin Muxing
+/** Offset 0x0A18 - DMIC<N> ClkB Pin Muxing
Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_*
**/
UINT32 PchHdaAudioLinkDmicClkBPinMux[2];
-/** Offset 0x09E8 - Enable HD Audio DSP
+/** Offset 0x0A20 - Enable HD Audio DSP
Enable/disable HD Audio DSP feature.
$EN_DIS
**/
UINT8 PchHdaDspEnable;
-/** Offset 0x09E9 - Reserved
+/** Offset 0x0A21 - Reserved
**/
- UINT8 Reserved38[3];
+ UINT8 Reserved40[3];
-/** Offset 0x09EC - DMIC<N> Data Pin Muxing
+/** Offset 0x0A24 - DMIC<N> Data Pin Muxing
Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_*
**/
UINT32 PchHdaAudioLinkDmicDataPinMux[2];
-/** Offset 0x09F4 - Enable HD Audio SSP0 Link
+/** Offset 0x0A2C - Enable HD Audio SSP0 Link
Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
**/
UINT8 PchHdaAudioLinkSspEnable[6];
-/** Offset 0x09FA - Enable HD Audio SoundWire#N Link
+/** Offset 0x0A32 - Enable HD Audio SoundWire#N Link
Enable/disable HD Audio SNDW#N link. Muxed with HDA.
**/
UINT8 PchHdaAudioLinkSndwEnable[4];
-/** Offset 0x09FE - iDisp-Link Frequency
+/** Offset 0x0A36 - iDisp-Link Frequency
iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz.
4: 96MHz, 3: 48MHz
**/
UINT8 PchHdaIDispLinkFrequency;
-/** Offset 0x09FF - Reserved
+/** Offset 0x0A37 - Reserved
**/
- UINT8 Reserved39;
+ UINT8 Reserved41;
-/** Offset 0x0A00 - iDisp-Link T-mode
+/** Offset 0x0A38 - iDisp-Link T-mode
iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T
0: 2T, 2: 4T, 3: 8T, 4: 16T
**/
UINT8 PchHdaIDispLinkTmode;
-/** Offset 0x0A01 - iDisplay Audio Codec disconnection
+/** Offset 0x0A39 - iDisplay Audio Codec disconnection
0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable.
$EN_DIS
**/
UINT8 PchHdaIDispCodecDisconnect;
-/** Offset 0x0A02 - Reserved
+/** Offset 0x0A3A - Reserved
**/
- UINT8 Reserved40[6];
+ UINT8 Reserved42[6];
-/** Offset 0x0A08 - CNVi DDR RFI Mitigation
+/** Offset 0x0A40 - CNVi DDR RFI Mitigation
Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE
$EN_DIS
**/
UINT8 CnviDdrRfim;
-/** Offset 0x0A09 - Reserved
+/** Offset 0x0A41 - Reserved
**/
- UINT8 Reserved41[11];
+ UINT8 Reserved43[11];
-/** Offset 0x0A14 - Debug Interfaces
+/** Offset 0x0A4C - Debug Interfaces
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
BIT2 - Not used.
**/
UINT8 PcdDebugInterfaceFlags;
-/** Offset 0x0A15 - Serial Io Uart Debug Controller Number
+/** Offset 0x0A4D - Serial Io Uart Debug Controller Number
Select SerialIo Uart Controller for debug.
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
**/
UINT8 SerialIoUartDebugControllerNumber;
-/** Offset 0x0A16 - Serial Io Uart Debug Auto Flow
+/** Offset 0x0A4E - Serial Io Uart Debug Auto Flow
Enables UART hardware flow control, CTS and RTS lines.
$EN_DIS
**/
UINT8 SerialIoUartDebugAutoFlow;
-/** Offset 0x0A17 - Reserved
+/** Offset 0x0A4F - Reserved
**/
- UINT8 Reserved42;
+ UINT8 Reserved44;
-/** Offset 0x0A18 - Serial Io Uart Debug BaudRate
+/** Offset 0x0A50 - Serial Io Uart Debug BaudRate
Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600,
19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000
**/
UINT32 SerialIoUartDebugBaudRate;
-/** Offset 0x0A1C - Serial Io Uart Debug Parity
+/** Offset 0x0A54 - Serial Io Uart Debug Parity
Set default Parity.
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
**/
UINT8 SerialIoUartDebugParity;
-/** Offset 0x0A1D - Serial Io Uart Debug Stop Bits
+/** Offset 0x0A55 - Serial Io Uart Debug Stop Bits
Set default stop bits.
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
**/
UINT8 SerialIoUartDebugStopBits;
-/** Offset 0x0A1E - Serial Io Uart Debug Data Bits
+/** Offset 0x0A56 - Serial Io Uart Debug Data Bits
Set default word length. 0: Default, 5,6,7,8
5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS
**/
UINT8 SerialIoUartDebugDataBits;
-/** Offset 0x0A1F - Reserved
+/** Offset 0x0A57 - Reserved
**/
- UINT8 Reserved43;
+ UINT8 Reserved45;
-/** Offset 0x0A20 - Serial Io Uart Debug Mmio Base
+/** Offset 0x0A58 - Serial Io Uart Debug Mmio Base
Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode
= SerialIoUartPci.
**/
UINT32 SerialIoUartDebugMmioBase;
-/** Offset 0x0A24 - ISA Serial Base selection
+/** Offset 0x0A5C - ISA Serial Base selection
Select ISA Serial Base address. Default is 0x3F8.
0:0x3F8, 1:0x2F8
**/
UINT8 PcdIsaSerialUartBase;
-/** Offset 0x0A25 - Reserved
+/** Offset 0x0A5D - Reserved
**/
- UINT8 Reserved44;
+ UINT8 Reserved46;
-/** Offset 0x0A26 - Ring PLL voltage offset
+/** Offset 0x0A5E - Ring PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 RingPllVoltageOffset;
-/** Offset 0x0A27 - System Agent PLL voltage offset
+/** Offset 0x0A5F - System Agent PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 SaPllVoltageOffset;
-/** Offset 0x0A28 - Reserved
+/** Offset 0x0A60 - Reserved
**/
- UINT8 Reserved45;
+ UINT8 Reserved47;
-/** Offset 0x0A29 - Memory Controller PLL voltage offset
+/** Offset 0x0A61 - Memory Controller PLL voltage offset
Core PLL voltage offset. <b>0: No offset</b>. Range 0-15
**/
UINT8 McPllVoltageOffset;
-/** Offset 0x0A2A - TCSS Thunderbolt PCIE Root Port 0 Enable
+/** Offset 0x0A62 - TCSS Thunderbolt PCIE Root Port 0 Enable
Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie0En;
-/** Offset 0x0A2B - TCSS Thunderbolt PCIE Root Port 1 Enable
+/** Offset 0x0A63 - TCSS Thunderbolt PCIE Root Port 1 Enable
Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie1En;
-/** Offset 0x0A2C - TCSS Thunderbolt PCIE Root Port 2 Enable
+/** Offset 0x0A64 - TCSS Thunderbolt PCIE Root Port 2 Enable
Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie2En;
-/** Offset 0x0A2D - TCSS Thunderbolt PCIE Root Port 3 Enable
+/** Offset 0x0A65 - TCSS Thunderbolt PCIE Root Port 3 Enable
Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssItbtPcie3En;
-/** Offset 0x0A2E - TCSS USB HOST (xHCI) Enable
+/** Offset 0x0A66 - TCSS USB HOST (xHCI) Enable
Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below
$EN_DIS
**/
UINT8 TcssXhciEn;
-/** Offset 0x0A2F - TCSS USB DEVICE (xDCI) Enable
+/** Offset 0x0A67 - TCSS USB DEVICE (xDCI) Enable
Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled
$EN_DIS
**/
UINT8 TcssXdciEn;
-/** Offset 0x0A30 - TCSS DMA0 Enable
+/** Offset 0x0A68 - TCSS DMA0 Enable
Set TCSS DMA0. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma0En;
-/** Offset 0x0A31 - TCSS DMA1 Enable
+/** Offset 0x0A69 - TCSS DMA1 Enable
Set TCSS DMA1. 0:Disabled 1:Enabled
$EN_DIS
**/
UINT8 TcssDma1En;
-/** Offset 0x0A32 - PcdSerialDebugBaudRate
+/** Offset 0x0A6A - PcdSerialDebugBaudRate
Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200.
3:9600, 4:19200, 6:56700, 7:115200
**/
UINT8 PcdSerialDebugBaudRate;
-/** Offset 0x0A33 - HobBufferSize
+/** Offset 0x0A6B - HobBufferSize
Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB
total HOB size).
0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value
**/
UINT8 HobBufferSize;
-/** Offset 0x0A34 - Early Command Training
+/** Offset 0x0A6C - Early Command Training
Enables/Disable Early Command Training
$EN_DIS
**/
UINT8 ECT;
-/** Offset 0x0A35 - SenseAmp Offset Training
+/** Offset 0x0A6D - SenseAmp Offset Training
Enables/Disable SenseAmp Offset Training
$EN_DIS
**/
UINT8 SOT;
-/** Offset 0x0A36 - Early ReadMPR Timing Centering 2D
+/** Offset 0x0A6E - Early ReadMPR Timing Centering 2D
Enables/Disable Early ReadMPR Timing Centering 2D
$EN_DIS
**/
UINT8 ERDMPRTC2D;
-/** Offset 0x0A37 - Read MPR Training
+/** Offset 0x0A6F - Read MPR Training
Enables/Disable Read MPR Training
$EN_DIS
**/
UINT8 RDMPRT;
-/** Offset 0x0A38 - Receive Enable Training
+/** Offset 0x0A70 - Receive Enable Training
Enables/Disable Receive Enable Training
$EN_DIS
**/
UINT8 RCVET;
-/** Offset 0x0A39 - Jedec Write Leveling
+/** Offset 0x0A71 - Jedec Write Leveling
Enables/Disable Jedec Write Leveling
$EN_DIS
**/
UINT8 JWRL;
-/** Offset 0x0A3A - Early Write Time Centering 2D
+/** Offset 0x0A72 - Early Write Time Centering 2D
Enables/Disable Early Write Time Centering 2D
$EN_DIS
**/
UINT8 EWRTC2D;
-/** Offset 0x0A3B - Early Read Time Centering 2D
+/** Offset 0x0A73 - Early Read Time Centering 2D
Enables/Disable Early Read Time Centering 2D
$EN_DIS
**/
UINT8 ERDTC2D;
-/** Offset 0x0A3C - Reserved
+/** Offset 0x0A74 - Reserved
**/
- UINT8 Reserved46;
+ UINT8 Reserved48;
-/** Offset 0x0A3D - Write Timing Centering 1D
+/** Offset 0x0A75 - Write Timing Centering 1D
Enables/Disable Write Timing Centering 1D
$EN_DIS
**/
UINT8 WRTC1D;
-/** Offset 0x0A3E - Write Voltage Centering 1D
+/** Offset 0x0A76 - Write Voltage Centering 1D
Enables/Disable Write Voltage Centering 1D
$EN_DIS
**/
UINT8 WRVC1D;
-/** Offset 0x0A3F - Read Timing Centering 1D
+/** Offset 0x0A77 - Read Timing Centering 1D
Enables/Disable Read Timing Centering 1D
$EN_DIS
**/
UINT8 RDTC1D;
-/** Offset 0x0A40 - Read Voltage Centering 1D
+/** Offset 0x0A78 - Read Voltage Centering 1D
Enable/Disable Read Voltage Centering 1D
$EN_DIS
**/
UINT8 RDVC1D;
-/** Offset 0x0A41 - Reserved
+/** Offset 0x0A79 - Reserved
**/
- UINT8 Reserved47[2];
+ UINT8 Reserved49[2];
-/** Offset 0x0A43 - Read ODT Training
+/** Offset 0x0A7B - Read ODT Training
Enables/Disable Read ODT Training
$EN_DIS
**/
UINT8 RDODTT;
-/** Offset 0x0A44 - Read Equalization Training
+/** Offset 0x0A7C - Read Equalization Training
Enables/Disable Read Equalization Training
$EN_DIS
**/
UINT8 RDEQT;
-/** Offset 0x0A45 - Reserved
+/** Offset 0x0A7D - Reserved
**/
- UINT8 Reserved48;
+ UINT8 Reserved50;
-/** Offset 0x0A46 - Write Timing Centering 2D
+/** Offset 0x0A7E - Write Timing Centering 2D
Enables/Disable Write Timing Centering 2D
$EN_DIS
**/
UINT8 WRTC2D;
-/** Offset 0x0A47 - Read Timing Centering 2D
+/** Offset 0x0A7F - Read Timing Centering 2D
Enables/Disable Read Timing Centering 2D
$EN_DIS
**/
UINT8 RDTC2D;
-/** Offset 0x0A48 - Write Voltage Centering 2D
+/** Offset 0x0A80 - Write Voltage Centering 2D
Enables/Disable Write Voltage Centering 2D
$EN_DIS
**/
UINT8 WRVC2D;
-/** Offset 0x0A49 - Read Voltage Centering 2D
+/** Offset 0x0A81 - Read Voltage Centering 2D
Enables/Disable Read Voltage Centering 2D
$EN_DIS
**/
UINT8 RDVC2D;
-/** Offset 0x0A4A - Reserved
+/** Offset 0x0A82 - Reserved
**/
- UINT8 Reserved49;
+ UINT8 Reserved51;
-/** Offset 0x0A4B - Command Voltage Centering
+/** Offset 0x0A83 - Command Voltage Centering
Enables/Disable Command Voltage Centering
$EN_DIS
**/
UINT8 CMDVC;
-/** Offset 0x0A4C - Late Command Training
+/** Offset 0x0A84 - Late Command Training
Enables/Disable Late Command Training
$EN_DIS
**/
UINT8 LCT;
-/** Offset 0x0A4D - Turn Around Timing Training
+/** Offset 0x0A85 - Turn Around Timing Training
Enables/Disable Turn Around Timing Training
$EN_DIS
**/
UINT8 TAT;
-/** Offset 0x0A4E - Rank Margin Tool
+/** Offset 0x0A86 - Rank Margin Tool
Enable/disable Rank Margin Tool
$EN_DIS
**/
UINT8 RMT;
-/** Offset 0x0A4F - Reserved
+/** Offset 0x0A87 - Reserved
**/
- UINT8 Reserved50;
+ UINT8 Reserved52;
-/** Offset 0x0A50 - DIMM SPD Alias Test
+/** Offset 0x0A88 - DIMM SPD Alias Test
Enables/Disable DIMM SPD Alias Test
$EN_DIS
**/
UINT8 ALIASCHK;
-/** Offset 0x0A51 - Retrain Margin Check
+/** Offset 0x0A89 - Retrain Margin Check
Enables/Disable Retrain Margin Check
$EN_DIS
**/
UINT8 RMC;
-/** Offset 0x0A52 - Reserved
+/** Offset 0x0A8A - Reserved
**/
- UINT8 Reserved51;
+ UINT8 Reserved53;
-/** Offset 0x0A53 - Dimm ODT Training
+/** Offset 0x0A8B - Dimm ODT Training
Enables/Disable Dimm ODT Training
$EN_DIS
**/
UINT8 DIMMODTT;
-/** Offset 0x0A54 - DIMM RON Training
+/** Offset 0x0A8C - DIMM RON Training
Enables/Disable DIMM RON Training
$EN_DIS
**/
UINT8 DIMMRONT;
-/** Offset 0x0A55 - TxDqTCO Comp Training
+/** Offset 0x0A8D - TxDqTCO Comp Training
Enable/Disable TxDqTCO Comp Training
$EN_DIS
**/
UINT8 TXTCO;
-/** Offset 0x0A56 - ClkTCO Comp Training
+/** Offset 0x0A8E - ClkTCO Comp Training
Enable/Disable ClkTCO Comp Training
$EN_DIS
**/
UINT8 CLKTCO;
-/** Offset 0x0A57 - CMD Slew Rate Training
+/** Offset 0x0A8F - CMD Slew Rate Training
Enable/Disable CMD Slew Rate Training
$EN_DIS
**/
UINT8 CMDSR;
-/** Offset 0x0A58 - Reserved
+/** Offset 0x0A90 - Reserved
**/
- UINT8 Reserved52[2];
+ UINT8 Reserved54[2];
-/** Offset 0x0A5A - DIMM CA ODT Training
+/** Offset 0x0A92 - DIMM CA ODT Training
Enable/Disable DIMM CA ODT Training
$EN_DIS
**/
UINT8 DIMMODTCA;
-/** Offset 0x0A5B - Reserved
+/** Offset 0x0A93 - Reserved
**/
- UINT8 Reserved53[3];
+ UINT8 Reserved55[3];
-/** Offset 0x0A5E - Read Vref Decap Training
+/** Offset 0x0A96 - Read Vref Decap Training
Enable/Disable Read Vref Decap Training
$EN_DIS
**/
UINT8 RDVREFDC;
-/** Offset 0x0A5F - Vddq Training
+/** Offset 0x0A97 - Vddq Training
Enable/Disable Vddq Training
$EN_DIS
**/
UINT8 VDDQT;
-/** Offset 0x0A60 - Rank Margin Tool Per Bit
+/** Offset 0x0A98 - Rank Margin Tool Per Bit
Enable/Disable Rank Margin Tool Per Bit
$EN_DIS
**/
UINT8 RMTBIT;
-/** Offset 0x0A61 - Reserved
+/** Offset 0x0A99 - Reserved
**/
- UINT8 Reserved54[4];
+ UINT8 Reserved56[4];
-/** Offset 0x0A65 - Duty Cycle Correction Training
+/** Offset 0x0A9D - Duty Cycle Correction Training
Enable/Disable Duty Cycle Correction Training
$EN_DIS
**/
UINT8 DCC;
-/** Offset 0x0A66 - Reserved
+/** Offset 0x0A9E - Reserved
**/
- UINT8 Reserved55[17];
+ UINT8 Reserved57[17];
-/** Offset 0x0A77 - ECC Support
+/** Offset 0x0AAF - ECC Support
Enables/Disable ECC Support
$EN_DIS
**/
UINT8 EccSupport;
-/** Offset 0x0A78 - Ibecc
+/** Offset 0x0AB0 - Ibecc
In-Band ECC Support
$EN_DIS
**/
UINT8 Ibecc;
-/** Offset 0x0A79 - IbeccParity
+/** Offset 0x0AB1 - IbeccParity
In-Band ECC Parity Control
$EN_DIS
**/
UINT8 IbeccParity;
-/** Offset 0x0A7A - IbeccOperationMode
+/** Offset 0x0AB2 - IbeccOperationMode
In-Band ECC Operation Mode
0:Protect base on address range, 1: Non-protected, 2: All protected
**/
UINT8 IbeccOperationMode;
-/** Offset 0x0A7B - IbeccProtectedRegionEnable
+/** Offset 0x0AB3 - IbeccProtectedRegionEnable
In-Band ECC Protected Region Enable
$EN_DIS
**/
UINT8 IbeccProtectedRegionEnable[8];
-/** Offset 0x0A83 - Reserved
+/** Offset 0x0ABB - Reserved
**/
- UINT8 Reserved56;
+ UINT8 Reserved58;
-/** Offset 0x0A84 - IbeccProtectedRegionBases
+/** Offset 0x0ABC - IbeccProtectedRegionBases
IBECC Protected Region Bases per IBECC instance
**/
UINT16 IbeccProtectedRegionBase[8];
-/** Offset 0x0A94 - IbeccProtectedRegionMasks
+/** Offset 0x0ACC - IbeccProtectedRegionMasks
IBECC Protected Region Masks
**/
UINT16 IbeccProtectedRegionMask[8];
-/** Offset 0x0AA4 - IbeccProtectedRegionOverallBases
+/** Offset 0x0ADC - IbeccProtectedRegionOverallBases
IBECC Protected Region Bases based on enabled IBECC instance
**/
UINT16 IbeccProtectedRegionOverallBase[8];
-/** Offset 0x0AB4 - Memory Remap
+/** Offset 0x0AEC - Memory Remap
Enables/Disable Memory Remap
$EN_DIS
**/
UINT8 RemapEnable;
-/** Offset 0x0AB5 - Rank Interleave support
+/** Offset 0x0AED - Rank Interleave support
Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at
the same time.
$EN_DIS
**/
UINT8 RankInterleave;
-/** Offset 0x0AB6 - Enhanced Interleave support
+/** Offset 0x0AEE - Enhanced Interleave support
Enables/Disable Enhanced Interleave support
$EN_DIS
**/
UINT8 EnhancedInterleave;
-/** Offset 0x0AB7 - Ch Hash Support
+/** Offset 0x0AEF - Ch Hash Support
Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode
$EN_DIS
**/
UINT8 ChHashEnable;
-/** Offset 0x0AB8 - Extern Therm Status
+/** Offset 0x0AF0 - Extern Therm Status
Enables/Disable Extern Therm Status
$EN_DIS
**/
UINT8 EnableExtts;
-/** Offset 0x0AB9 - DDR PowerDown and idle counter
+/** Offset 0x0AF1 - DDR PowerDown and idle counter
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
$EN_DIS
**/
UINT8 EnablePwrDn;
-/** Offset 0x0ABA - DDR PowerDown and idle counter
+/** Offset 0x0AF2 - DDR PowerDown and idle counter
Enables/Disable DDR PowerDown and idle counter(For LPDDR Only)
$EN_DIS
**/
UINT8 EnablePwrDnLpddr;
-/** Offset 0x0ABB - SelfRefresh Enable
+/** Offset 0x0AF3 - SelfRefresh Enable
Enables/Disable SelfRefresh Enable
$EN_DIS
**/
UINT8 SrefCfgEna;
-/** Offset 0x0ABC - Throttler CKEMin Defeature
+/** Offset 0x0AF4 - Throttler CKEMin Defeature
Enables/Disable Throttler CKEMin Defeature(For LPDDR Only)
$EN_DIS
**/
UINT8 ThrtCkeMinDefeatLpddr;
-/** Offset 0x0ABD - Throttler CKEMin Defeature
+/** Offset 0x0AF5 - Throttler CKEMin Defeature
Enables/Disable Throttler CKEMin Defeature
$EN_DIS
**/
UINT8 ThrtCkeMinDefeat;
-/** Offset 0x0ABE - Reserved
+/** Offset 0x0AF6 - Reserved
**/
- UINT8 Reserved57;
+ UINT8 Reserved59;
-/** Offset 0x0ABF - Exit On Failure (MRC)
+/** Offset 0x0AF7 - Exit On Failure (MRC)
Enables/Disable Exit On Failure (MRC)
$EN_DIS
**/
UINT8 ExitOnFailure;
-/** Offset 0x0AC0 - Reserved
+/** Offset 0x0AF8 - Reserved
**/
- UINT8 Reserved58[4];
+ UINT8 Reserved60[4];
-/** Offset 0x0AC4 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
+/** Offset 0x0AFC - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP
$EN_DIS
**/
UINT8 Ddr4DdpSharedZq;
-/** Offset 0x0AC5 - Ch Hash Interleaved Bit
+/** Offset 0x0AFD - Ch Hash Interleaved Bit
Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave
the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8
0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13
**/
UINT8 ChHashInterleaveBit;
-/** Offset 0x0AC6 - Ch Hash Mask
+/** Offset 0x0AFE - Ch Hash Mask
Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to
BITS [19:6] Default is 0x30CC
**/
UINT16 ChHashMask;
-/** Offset 0x0AC8 - Base reference clock value
+/** Offset 0x0B00 - Base reference clock value
Base reference clock value, in Hertz(Default is 125Hz)
100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz
**/
UINT32 BClkFrequency;
-/** Offset 0x0ACC - EPG DIMM Idd3N
+/** Offset 0x0B04 - EPG DIMM Idd3N
Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on
a per DIMM basis. Default is 26
**/
UINT16 Idd3n;
-/** Offset 0x0ACE - EPG DIMM Idd3P
+/** Offset 0x0B06 - EPG DIMM Idd3P
Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated
on a per DIMM basis. Default is 11
**/
UINT16 Idd3p;
-/** Offset 0x0AD0 - CMD Normalization
+/** Offset 0x0B08 - CMD Normalization
Enable/Disable CMD Normalization
$EN_DIS
**/
UINT8 CMDNORM;
-/** Offset 0x0AD1 - Early DQ Write Drive Strength and Equalization Training
+/** Offset 0x0B09 - Early DQ Write Drive Strength and Equalization Training
Enable/Disable Early DQ Write Drive Strength and Equalization Training
$EN_DIS
**/
UINT8 EWRDSEQ;
-/** Offset 0x0AD2 - Idle Energy Mc0Ch0Dimm0
+/** Offset 0x0B0A - Idle Energy Mc0Ch0Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch0Dimm0;
-/** Offset 0x0AD3 - Idle Energy Mc0Ch0Dimm1
+/** Offset 0x0B0B - Idle Energy Mc0Ch0Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch0Dimm1;
-/** Offset 0x0AD4 - Idle Energy Mc0Ch1Dimm0
+/** Offset 0x0B0C - Idle Energy Mc0Ch1Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch1Dimm0;
-/** Offset 0x0AD5 - Idle Energy Mc0Ch1Dimm1
+/** Offset 0x0B0D - Idle Energy Mc0Ch1Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc0Ch1Dimm1;
-/** Offset 0x0AD6 - Idle Energy Mc1Ch0Dimm0
+/** Offset 0x0B0E - Idle Energy Mc1Ch0Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch0Dimm0;
-/** Offset 0x0AD7 - Idle Energy Mc1Ch0Dimm1
+/** Offset 0x0B0F - Idle Energy Mc1Ch0Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch0Dimm1;
-/** Offset 0x0AD8 - Idle Energy Mc1Ch1Dimm0
+/** Offset 0x0B10 - Idle Energy Mc1Ch1Dimm0
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch1Dimm0;
-/** Offset 0x0AD9 - Idle Energy Mc1Ch1Dimm1
+/** Offset 0x0B11 - Idle Energy Mc1Ch1Dimm1
Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def)
**/
UINT8 IdleEnergyMc1Ch1Dimm1;
-/** Offset 0x0ADA - PowerDown Energy Mc0Ch0Dimm0
+/** Offset 0x0B12 - PowerDown Energy Mc0Ch0Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch0Dimm0;
-/** Offset 0x0ADB - PowerDown Energy Mc0Ch0Dimm1
+/** Offset 0x0B13 - PowerDown Energy Mc0Ch0Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch0Dimm1;
-/** Offset 0x0ADC - PowerDown Energy Mc0Ch1Dimm0
+/** Offset 0x0B14 - PowerDown Energy Mc0Ch1Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch1Dimm0;
-/** Offset 0x0ADD - PowerDown Energy Mc0Ch1Dimm1
+/** Offset 0x0B15 - PowerDown Energy Mc0Ch1Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc0Ch1Dimm1;
-/** Offset 0x0ADE - PowerDown Energy Mc1Ch0Dimm0
+/** Offset 0x0B16 - PowerDown Energy Mc1Ch0Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch0Dimm0;
-/** Offset 0x0ADF - PowerDown Energy Mc1Ch0Dimm1
+/** Offset 0x0B17 - PowerDown Energy Mc1Ch0Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch0Dimm1;
-/** Offset 0x0AE0 - PowerDown Energy Mc1Ch1Dimm0
+/** Offset 0x0B18 - PowerDown Energy Mc1Ch1Dimm0
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch1Dimm0;
-/** Offset 0x0AE1 - PowerDown Energy Mc1Ch1Dimm1
+/** Offset 0x0B19 - PowerDown Energy Mc1Ch1Dimm1
PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def)
**/
UINT8 PdEnergyMc1Ch1Dimm1;
-/** Offset 0x0AE2 - Activate Energy Mc0Ch0Dimm0
+/** Offset 0x0B1A - Activate Energy Mc0Ch0Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch0Dimm0;
-/** Offset 0x0AE3 - Activate Energy Mc0Ch0Dimm1
+/** Offset 0x0B1B - Activate Energy Mc0Ch0Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch0Dimm1;
-/** Offset 0x0AE4 - Activate Energy Mc0Ch1Dimm0
+/** Offset 0x0B1C - Activate Energy Mc0Ch1Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch1Dimm0;
-/** Offset 0x0AE5 - Activate Energy Mc0Ch1Dimm1
+/** Offset 0x0B1D - Activate Energy Mc0Ch1Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc0Ch1Dimm1;
-/** Offset 0x0AE6 - Activate Energy Mc1Ch0Dimm0
+/** Offset 0x0B1E - Activate Energy Mc1Ch0Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch0Dimm0;
-/** Offset 0x0AE7 - Activate Energy Mc1Ch0Dimm1
+/** Offset 0x0B1F - Activate Energy Mc1Ch0Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch0Dimm1;
-/** Offset 0x0AE8 - Activate Energy Mc1Ch1Dimm0
+/** Offset 0x0B20 - Activate Energy Mc1Ch1Dimm0
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch1Dimm0;
-/** Offset 0x0AE9 - Activate Energy Mc1Ch1Dimm1
+/** Offset 0x0B21 - Activate Energy Mc1Ch1Dimm1
Activate Energy Contribution, range[255;0],(172= Def)
**/
UINT8 ActEnergyMc1Ch1Dimm1;
-/** Offset 0x0AEA - Read Energy Mc0Ch0Dimm0
+/** Offset 0x0B22 - Read Energy Mc0Ch0Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch0Dimm0;
-/** Offset 0x0AEB - Read Energy Mc0Ch0Dimm1
+/** Offset 0x0B23 - Read Energy Mc0Ch0Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch0Dimm1;
-/** Offset 0x0AEC - Read Energy Mc0Ch1Dimm0
+/** Offset 0x0B24 - Read Energy Mc0Ch1Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch1Dimm0;
-/** Offset 0x0AED - Read Energy Mc0Ch1Dimm1
+/** Offset 0x0B25 - Read Energy Mc0Ch1Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc0Ch1Dimm1;
-/** Offset 0x0AEE - Read Energy Mc1Ch0Dimm0
+/** Offset 0x0B26 - Read Energy Mc1Ch0Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch0Dimm0;
-/** Offset 0x0AEF - Read Energy Mc1Ch0Dimm1
+/** Offset 0x0B27 - Read Energy Mc1Ch0Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch0Dimm1;
-/** Offset 0x0AF0 - Read Energy Mc1Ch1Dimm0
+/** Offset 0x0B28 - Read Energy Mc1Ch1Dimm0
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch1Dimm0;
-/** Offset 0x0AF1 - Read Energy Mc1Ch1Dimm1
+/** Offset 0x0B29 - Read Energy Mc1Ch1Dimm1
Read Energy Contribution, range[255;0],(212= Def)
**/
UINT8 RdEnergyMc1Ch1Dimm1;
-/** Offset 0x0AF2 - Write Energy Mc0Ch0Dimm0
+/** Offset 0x0B2A - Write Energy Mc0Ch0Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch0Dimm0;
-/** Offset 0x0AF3 - Write Energy Mc0Ch0Dimm1
+/** Offset 0x0B2B - Write Energy Mc0Ch0Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch0Dimm1;
-/** Offset 0x0AF4 - Write Energy Mc0Ch1Dimm0
+/** Offset 0x0B2C - Write Energy Mc0Ch1Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch1Dimm0;
-/** Offset 0x0AF5 - Write Energy Mc0Ch1Dimm1
+/** Offset 0x0B2D - Write Energy Mc0Ch1Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc0Ch1Dimm1;
-/** Offset 0x0AF6 - Write Energy Mc1Ch0Dimm0
+/** Offset 0x0B2E - Write Energy Mc1Ch0Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch0Dimm0;
-/** Offset 0x0AF7 - Write Energy Mc1Ch0Dimm1
+/** Offset 0x0B2F - Write Energy Mc1Ch0Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch0Dimm1;
-/** Offset 0x0AF8 - Write Energy Mc1Ch1Dimm0
+/** Offset 0x0B30 - Write Energy Mc1Ch1Dimm0
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch1Dimm0;
-/** Offset 0x0AF9 - Write Energy Mc1Ch1Dimm1
+/** Offset 0x0B31 - Write Energy Mc1Ch1Dimm1
Write Energy Contribution, range[255;0],(221= Def)
**/
UINT8 WrEnergyMc1Ch1Dimm1;
-/** Offset 0x0AFA - Throttler CKEMin Timer
+/** Offset 0x0B32 - Throttler CKEMin Timer
Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4).
Dfault is 0x00
**/
UINT8 ThrtCkeMinTmr;
-/** Offset 0x0AFB - Reserved
+/** Offset 0x0B33 - Reserved
**/
- UINT8 Reserved59[2];
+ UINT8 Reserved61[2];
-/** Offset 0x0AFD - Rapl Power Floor Ch0
+/** Offset 0x0B35 - Rapl Power Floor Ch0
Power budget ,range[255;0],(0= 5.3W Def)
**/
UINT8 RaplPwrFlCh0;
-/** Offset 0x0AFE - Rapl Power Floor Ch1
+/** Offset 0x0B36 - Rapl Power Floor Ch1
Power budget ,range[255;0],(0= 5.3W Def)
**/
UINT8 RaplPwrFlCh1;
-/** Offset 0x0AFF - Command Rate Support
+/** Offset 0x0B37 - Command Rate Support
CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs
0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS
**/
UINT8 EnCmdRate;
-/** Offset 0x0B00 - Reserved
+/** Offset 0x0B38 - Reserved
**/
- UINT8 Reserved60;
+ UINT8 Reserved62;
-/** Offset 0x0B01 - Energy Performance Gain
+/** Offset 0x0B39 - Energy Performance Gain
Enable/disable Energy Performance Gain. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 EpgEnable;
-/** Offset 0x0B02 - Reserved
+/** Offset 0x0B3A - Reserved
**/
- UINT8 Reserved61;
+ UINT8 Reserved63;
-/** Offset 0x0B03 - User Manual Threshold
+/** Offset 0x0B3B - User Manual Threshold
Disabled: Predefined threshold will be used.\n
Enabled: User Input will be used.
$EN_DIS
**/
UINT8 UserThresholdEnable;
-/** Offset 0x0B04 - User Manual Budget
+/** Offset 0x0B3C - User Manual Budget
Disabled: Configuration of memories will defined the Budget value.\n
Enabled: User Input will be used.
$EN_DIS
**/
UINT8 UserBudgetEnable;
-/** Offset 0x0B05 - Power Down Mode
+/** Offset 0x0B3D - Reserved
+**/
+ UINT8 Reserved64;
+
+/** Offset 0x0B3E - Power Down Mode
This option controls command bus tristating during idle periods
0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto
**/
UINT8 PowerDownMode;
-/** Offset 0x0B06 - Pwr Down Idle Timer
+/** Offset 0x0B3F - Pwr Down Idle Timer
The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means
AUTO: 64 for ULX/ULT, 128 for DT/Halo
**/
UINT8 PwdwnIdleCounter;
-/** Offset 0x0B07 - Page Close Idle Timeout
+/** Offset 0x0B40 - Page Close Idle Timeout
This option controls Page Close Idle Timeout
0:Enabled, 1:Disabled
**/
UINT8 DisPgCloseIdleTimeout;
-/** Offset 0x0B08 - Bitmask of ranks that have CA bus terminated
+/** Offset 0x0B41 - Bitmask of ranks that have CA bus terminated
Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default,
Rank0 is terminating and Rank1 is non-terminating</b>
**/
UINT8 CmdRanksTerminated;
-/** Offset 0x0B09 - PcdSerialDebugLevel
+/** Offset 0x0B42 - PcdSerialDebugLevel
Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -2668,72 +2680,76 @@ typedef struct {
**/
UINT8 PcdSerialDebugLevel;
-/** Offset 0x0B0A - Reserved
+/** Offset 0x0B43 - Reserved
**/
- UINT8 Reserved62[7];
+ UINT8 Reserved65[8];
-/** Offset 0x0B11 - Ask MRC to clear memory content
+/** Offset 0x0B4B - Ask MRC to clear memory content
Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory.
$EN_DIS
**/
UINT8 CleanMemory;
-/** Offset 0x0B12 - TCSS USB Port Enable
+/** Offset 0x0B4C - TCSS USB Port Enable
Bitmap for per port enabling
**/
UINT8 UsbTcPortEnPreMem;
-/** Offset 0x0B13 - Reserved
+/** Offset 0x0B4D - Reserved
**/
- UINT8 Reserved63;
+ UINT8 Reserved66;
-/** Offset 0x0B14 - Post Code Output Port
+/** Offset 0x0B4E - Post Code Output Port
This option configures Post Code Output Port
**/
UINT16 PostCodeOutputPort;
-/** Offset 0x0B16 - RMTLoopCount
+/** Offset 0x0B50 - RMTLoopCount
Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO
**/
UINT8 RMTLoopCount;
-/** Offset 0x0B17 - Enable/Disable SA CRID
+/** Offset 0x0B51 - Enable/Disable SA CRID
Enable: SA CRID, Disable (Default): SA CRID
$EN_DIS
**/
UINT8 CridEnable;
-/** Offset 0x0B18 - BCLK RFI Frequency
+/** Offset 0x0B52 - Reserved
+**/
+ UINT8 Reserved67[2];
+
+/** Offset 0x0B54 - BCLK RFI Frequency
Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No
RFI Tuning</b>. Range is 98Mhz-100Mhz.
**/
UINT32 BclkRfiFreq[4];
-/** Offset 0x0B28 - Size of PCIe IMR.
+/** Offset 0x0B64 - Size of PCIe IMR.
Size of PCIe IMR in megabytes
**/
UINT16 PcieImrSize;
-/** Offset 0x0B2A - Enable PCIe IMR
+/** Offset 0x0B66 - Enable PCIe IMR
0: Disable(AUTO), 1: Enable
$EN_DIS
**/
UINT8 PcieImrEnabled;
-/** Offset 0x0B2B - Enable PCIe IMR
+/** Offset 0x0B67 - Enable PCIe IMR
1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select
the Root port location from PCH PCIe or SA PCIe
$EN_DIS
**/
UINT8 PcieImrRpLocation;
-/** Offset 0x0B2C - Root port number for IMR.
+/** Offset 0x0B68 - Root port number for IMR.
Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port
from 0 to 23 and if it is SA PCIe then select root port from 0 to 3
**/
UINT8 PcieImrRpSelection;
-/** Offset 0x0B2D - SerialDebugMrcLevel
+/** Offset 0x0B69 - SerialDebugMrcLevel
MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load,
Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings,
Info & Verbose.
@@ -2742,208 +2758,208 @@ typedef struct {
**/
UINT8 SerialDebugMrcLevel;
-/** Offset 0x0B2E - Reserved
+/** Offset 0x0B6A - Reserved
**/
- UINT8 Reserved64[13];
+ UINT8 Reserved68[13];
-/** Offset 0x0B3B - Command Pins Mapping
+/** Offset 0x0B77 - Command Pins Mapping
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending.
**/
UINT8 Lp5CccConfig;
-/** Offset 0x0B3C - Command Pins Mirrored
+/** Offset 0x0B78 - Command Pins Mirrored
BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller
1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror.
**/
UINT8 CmdMirror;
-/** Offset 0x0B3D - Reserved
+/** Offset 0x0B79 - Reserved
**/
- UINT8 Reserved65[4];
+ UINT8 Reserved69[4];
-/** Offset 0x0B41 - Skip external display device scanning
+/** Offset 0x0B7D - Skip external display device scanning
Enable: Do not scan for external display device, Disable (Default): Scan external
display devices
$EN_DIS
**/
UINT8 SkipExtGfxScan;
-/** Offset 0x0B42 - Generate BIOS Data ACPI Table
+/** Offset 0x0B7E - Generate BIOS Data ACPI Table
Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it
$EN_DIS
**/
UINT8 BdatEnable;
-/** Offset 0x0B43 - Lock PCU Thermal Management registers
+/** Offset 0x0B7F - Lock PCU Thermal Management registers
Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0
$EN_DIS
**/
UINT8 LockPTMregs;
-/** Offset 0x0B44 - Panel Power Enable
+/** Offset 0x0B80 - Panel Power Enable
Control for enabling/disabling VDD force bit (Required only for early enabling of
eDP panel). 0=Disable, 1(Default)=Enable
$EN_DIS
**/
UINT8 PanelPowerEnable;
-/** Offset 0x0B45 - BdatTestType
+/** Offset 0x0B81 - BdatTestType
Indicates the type of Memory Training data to populate into the BDAT ACPI table.
0:RMT per Rank, 1:RMT per Bit, 2:Margin2D
**/
UINT8 BdatTestType;
-/** Offset 0x0B46 - Reserved
+/** Offset 0x0B82 - Reserved
**/
- UINT8 Reserved66[2];
+ UINT8 Reserved70[2];
-/** Offset 0x0B48 - PMR Size
+/** Offset 0x0B84 - PMR Size
Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot
**/
UINT32 DmaBufferSize;
-/** Offset 0x0B4C - The policy for VTd driver behavior
+/** Offset 0x0B88 - The policy for VTd driver behavior
BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS
**/
UINT8 PreBootDmaMask;
-/** Offset 0x0B4D - Reserved
+/** Offset 0x0B89 - Reserved
**/
- UINT8 Reserved67[95];
+ UINT8 Reserved71[95];
-/** Offset 0x0BAC - TotalFlashSize
+/** Offset 0x0BE8 - TotalFlashSize
Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable
**/
UINT16 TotalFlashSize;
-/** Offset 0x0BAE - BiosSize
+/** Offset 0x0BEA - BiosSize
The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard !=
0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected
Range) so that a BIOS Update Script can be stored in the DPR.
**/
UINT16 BiosSize;
-/** Offset 0x0BB0 - Reserved
+/** Offset 0x0BEC - Reserved
**/
- UINT8 Reserved68[12];
+ UINT8 Reserved72[12];
-/** Offset 0x0BBC - Smbus dynamic power gating
+/** Offset 0x0BF8 - Smbus dynamic power gating
Disable or Enable Smbus dynamic power gating.
$EN_DIS
**/
UINT8 SmbusDynamicPowerGating;
-/** Offset 0x0BBD - Disable and Lock Watch Dog Register
+/** Offset 0x0BF9 - Disable and Lock Watch Dog Register
Set 1 to clear WDT status, then disable and lock WDT registers.
$EN_DIS
**/
UINT8 WdtDisableAndLock;
-/** Offset 0x0BBE - SMBUS SPD Write Disable
+/** Offset 0x0BFA - SMBUS SPD Write Disable
Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write
Disable bit. For security recommendations, SPD write disable bit must be set.
$EN_DIS
**/
UINT8 SmbusSpdWriteDisable;
-/** Offset 0x0BBF - Reserved
+/** Offset 0x0BFB - Reserved
**/
- UINT8 Reserved69[34];
+ UINT8 Reserved73[34];
-/** Offset 0x0BE1 - HECI Timeouts
+/** Offset 0x0C1D - HECI Timeouts
0: Disable, 1: Enable (Default) timeout check for HECI
$EN_DIS
**/
UINT8 HeciTimeouts;
-/** Offset 0x0BE2 - Force ME DID Init Status
+/** Offset 0x0C1E - Force ME DID Init Status
Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set
ME DID init stat value
$EN_DIS
**/
UINT8 DidInitStat;
-/** Offset 0x0BE3 - CPU Replaced Polling Disable
+/** Offset 0x0C1F - CPU Replaced Polling Disable
Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop
$EN_DIS
**/
UINT8 DisableCpuReplacedPolling;
-/** Offset 0x0BE4 - Check HECI message before send
+/** Offset 0x0C20 - Check HECI message before send
Test, 0: disable, 1: enable, Enable/Disable message check.
$EN_DIS
**/
UINT8 DisableMessageCheck;
-/** Offset 0x0BE5 - Skip MBP HOB
+/** Offset 0x0C21 - Skip MBP HOB
Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
$EN_DIS
**/
UINT8 SkipMbpHob;
-/** Offset 0x0BE6 - HECI2 Interface Communication
+/** Offset 0x0C22 - HECI2 Interface Communication
Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space.
$EN_DIS
**/
UINT8 HeciCommunication2;
-/** Offset 0x0BE7 - Enable KT device
+/** Offset 0x0C23 - Enable KT device
Test, 0: disable, 1: enable, Enable or Disable KT device.
$EN_DIS
**/
UINT8 KtDeviceEnable;
-/** Offset 0x0BE8 - Skip CPU replacement check
+/** Offset 0x0C24 - Skip CPU replacement check
Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check
$EN_DIS
**/
UINT8 SkipCpuReplacementCheck;
-/** Offset 0x0BE9 - Avx2 Voltage Guardband Scaling Factor
+/** Offset 0x0C25 - Avx2 Voltage Guardband Scaling Factor
AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in
1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx2VoltageScaleFactor;
-/** Offset 0x0BEA - Avx512 Voltage Guardband Scaling Factor
+/** Offset 0x0C26 - Avx512 Voltage Guardband Scaling Factor
AVX512 Voltage Guardband Scale factor applied to AVX512 workloads. Range is 0-200
in 1/100 units, where a value of 125 would apply a 1.25 scale factor.
**/
UINT8 Avx512VoltageScaleFactor;
-/** Offset 0x0BEB - Serial Io Uart Debug Mode
+/** Offset 0x0C27 - Serial Io Uart Debug Mode
Select SerialIo Uart Controller mode
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
4:SerialIoUartSkipInit
**/
UINT8 SerialIoUartDebugMode;
-/** Offset 0x0BEC - SerialIoUartDebugRxPinMux - FSPM
+/** Offset 0x0C28 - SerialIoUartDebugRxPinMux - FSPM
Select RX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugRxPinMux;
-/** Offset 0x0BF0 - SerialIoUartDebugTxPinMux - FSPM
+/** Offset 0x0C2C - SerialIoUartDebugTxPinMux - FSPM
Select TX pin muxing for SerialIo UART used for debug
**/
UINT32 SerialIoUartDebugTxPinMux;
-/** Offset 0x0BF4 - SerialIoUartDebugRtsPinMux - FSPM
+/** Offset 0x0C30 - SerialIoUartDebugRtsPinMux - FSPM
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
for possible values.
**/
UINT32 SerialIoUartDebugRtsPinMux;
-/** Offset 0x0BF8 - SerialIoUartDebugCtsPinMux - FSPM
+/** Offset 0x0C34 - SerialIoUartDebugCtsPinMux - FSPM
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
for possible values.
**/
UINT32 SerialIoUartDebugCtsPinMux;
-/** Offset 0x0BFC - Reserved
+/** Offset 0x0C38 - Reserved
**/
- UINT8 Reserved70[20];
+ UINT8 Reserved74[24];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@@ -2962,11 +2978,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
-/** Offset 0x0C10
+/** Offset 0x0C50
**/
UINT8 Rsvd500[6];
-/** Offset 0x0C16
+/** Offset 0x0C56
**/
UINT16 UpdTerminator;
} FSPM_UPD;
diff --git a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
index f9401293fb..f2debf0876 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
@@ -1,6 +1,6 @@
/** @file
-Copyright (c) 2022, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2023, Intel Corporation. All rights reserved.<BR>
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
@@ -1339,9 +1339,9 @@ typedef struct {
/** Offset 0x06E4 - Reserved
**/
- UINT8 Reserved33[14];
+ UINT8 Reserved33[4];
-/** Offset 0x06F2 - PpinSupport to view Protected Processor Inventory Number
+/** Offset 0x06E8 - PpinSupport to view Protected Processor Inventory Number
PPIN Feature Support to view Protected Processor Inventory Number. Disable to turn
off this feature. When 'PPIN Enable Mode' is selected, this shows second option
where feature can be enabled based on EOM (End of Manufacturing) flag or it is
@@ -1350,31 +1350,31 @@ typedef struct {
**/
UINT8 PpinSupport;
-/** Offset 0x06F3 - Reserved
+/** Offset 0x06E9 - Reserved
**/
UINT8 Reserved34;
-/** Offset 0x06F4 - Smbios Type4 Max Speed Override
+/** Offset 0x06EA - Smbios Type4 Max Speed Override
Provide the option for platform to override the MaxSpeed field of Smbios Type 4.
If this value is not zero, it dominates the field.
**/
UINT16 SmbiosType4MaxSpeedOverride;
-/** Offset 0x06F6 - Advanced Encryption Standard (AES) feature
+/** Offset 0x06EC - Advanced Encryption Standard (AES) feature
Enable or Disable Advanced Encryption Standard (AES) feature; </b>0: Disable; <b>1: Enable
$EN_DIS
**/
UINT8 AesEnable;
-/** Offset 0x06F7 - AvxDisable
+/** Offset 0x06ED - AvxDisable
Enable/Disable the AVX and AVX2 Instructions
0: Enable, 1: Disable
**/
UINT8 AvxDisable;
-/** Offset 0x06F8 - Reserved
+/** Offset 0x06EE - Reserved
**/
- UINT8 Reserved35[48];
+ UINT8 Reserved35[58];
/** Offset 0x0728 - Enable Power Optimizer
Enable DMI Power Optimizer on PCH side.
@@ -1676,380 +1676,385 @@ typedef struct {
**/
UINT8 PchPmWoWlanEnable;
-/** Offset 0x190F - PCH Pm Slp S3 Min Assert
+/** Offset 0x190F - Reserved
+**/
+ UINT8 Reserved41[4];
+
+/** Offset 0x1913 - PCH Pm Slp S3 Min Assert
SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
**/
UINT8 PchPmSlpS3MinAssert;
-/** Offset 0x1910 - PCH Pm Slp S4 Min Assert
+/** Offset 0x1914 - PCH Pm Slp S4 Min Assert
SLP_S4 Minimum Assertion Width Policy. Default is PchSlpS44s.
**/
UINT8 PchPmSlpS4MinAssert;
-/** Offset 0x1911 - PCH Pm Slp Sus Min Assert
+/** Offset 0x1915 - PCH Pm Slp Sus Min Assert
SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
**/
UINT8 PchPmSlpSusMinAssert;
-/** Offset 0x1912 - PCH Pm Slp A Min Assert
+/** Offset 0x1916 - PCH Pm Slp A Min Assert
SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
**/
UINT8 PchPmSlpAMinAssert;
-/** Offset 0x1913 - USB Overcurrent Override for VISA
+/** Offset 0x1917 - USB Overcurrent Override for VISA
This option overrides USB Over Current enablement state that USB OC will be disabled
after enabling this option. Enable when VISA pin is muxed with USB OC
$EN_DIS
**/
UINT8 PchEnableDbcObs;
-/** Offset 0x1914 - PCH Pm Slp Strch Sus Up
+/** Offset 0x1918 - PCH Pm Slp Strch Sus Up
Enable SLP_X Stretching After SUS Well Power Up.
$EN_DIS
**/
UINT8 PchPmSlpStrchSusUp;
-/** Offset 0x1915 - PCH Pm Slp Lan Low Dc
+/** Offset 0x1919 - PCH Pm Slp Lan Low Dc
Enable/Disable SLP_LAN# Low on DC Power.
$EN_DIS
**/
UINT8 PchPmSlpLanLowDc;
-/** Offset 0x1916 - PCH Pm Pwr Btn Override Period
+/** Offset 0x191A - PCH Pm Pwr Btn Override Period
PCH power button override period. 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s.
**/
UINT8 PchPmPwrBtnOverridePeriod;
-/** Offset 0x1917 - PCH Pm Disable Native Power Button
+/** Offset 0x191B - PCH Pm Disable Native Power Button
Power button native mode disable.
$EN_DIS
**/
UINT8 PchPmDisableNativePowerButton;
-/** Offset 0x1918 - PCH Pm ME_WAKE_STS
+/** Offset 0x191C - PCH Pm ME_WAKE_STS
Clear the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmMeWakeSts;
-/** Offset 0x1919 - PCH Pm WOL_OVR_WK_STS
+/** Offset 0x191D - PCH Pm WOL_OVR_WK_STS
Clear the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register.
$EN_DIS
**/
UINT8 PchPmWolOvrWkSts;
-/** Offset 0x191A - PCH Pm Reset Power Cycle Duration
+/** Offset 0x191E - PCH Pm Reset Power Cycle Duration
Could be customized in the unit of second. Please refer to EDS for all support settings.
0 is default, 1 is 1 second, 2 is 2 seconds, ...
**/
UINT8 PchPmPwrCycDur;
-/** Offset 0x191B - PCH Pm Pcie Pll Ssc
+/** Offset 0x191F - PCH Pm Pcie Pll Ssc
Specifies the Pcie Pll Spread Spectrum Percentage. The default is 0xFF: AUTO - No
BIOS override.
**/
UINT8 PchPmPciePllSsc;
-/** Offset 0x191C - PCH Legacy IO Low Latency Enable
+/** Offset 0x1920 - PCH Legacy IO Low Latency Enable
Set to enable low latency of legacy IO. <b>0: Disable</b>, 1: Enable
$EN_DIS
**/
UINT8 PchLegacyIoLowLatency;
-/** Offset 0x191D - PCH Sata Pwr Opt Enable
+/** Offset 0x1921 - PCH Sata Pwr Opt Enable
SATA Power Optimizer on PCH side.
$EN_DIS
**/
UINT8 SataPwrOptEnable;
-/** Offset 0x191E - PCH Sata eSATA Speed Limit
+/** Offset 0x1922 - PCH Sata eSATA Speed Limit
When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed.
$EN_DIS
**/
UINT8 EsataSpeedLimit;
-/** Offset 0x191F - PCH Sata Speed Limit
+/** Offset 0x1923 - PCH Sata Speed Limit
Indicates the maximum speed the SATA controller can support 0h: PchSataSpeedDefault.
**/
UINT8 SataSpeedLimit;
-/** Offset 0x1920 - Enable SATA Port HotPlug
+/** Offset 0x1924 - Enable SATA Port HotPlug
Enable SATA Port HotPlug.
**/
UINT8 SataPortsHotPlug[8];
-/** Offset 0x1928 - Enable SATA Port Interlock Sw
+/** Offset 0x192C - Enable SATA Port Interlock Sw
Enable SATA Port Interlock Sw.
**/
UINT8 SataPortsInterlockSw[8];
-/** Offset 0x1930 - Enable SATA Port External
+/** Offset 0x1934 - Enable SATA Port External
Enable SATA Port External.
**/
UINT8 SataPortsExternal[8];
-/** Offset 0x1938 - Enable SATA Port SpinUp
+/** Offset 0x193C - Enable SATA Port SpinUp
Enable the COMRESET initialization Sequence to the device.
**/
UINT8 SataPortsSpinUp[8];
-/** Offset 0x1940 - Enable SATA Port Solid State Drive
+/** Offset 0x1944 - Enable SATA Port Solid State Drive
0: HDD; 1: SSD.
**/
UINT8 SataPortsSolidStateDrive[8];
-/** Offset 0x1948 - Enable SATA Port Enable Dito Config
+/** Offset 0x194C - Enable SATA Port Enable Dito Config
Enable DEVSLP Idle Timeout settings (DmVal, DitoVal).
**/
UINT8 SataPortsEnableDitoConfig[8];
-/** Offset 0x1950 - Enable SATA Port DmVal
+/** Offset 0x1954 - Enable SATA Port DmVal
DITO multiplier. Default is 15.
**/
UINT8 SataPortsDmVal[8];
-/** Offset 0x1958 - Reserved
+/** Offset 0x195C - Reserved
**/
- UINT8 Reserved41[2];
+ UINT8 Reserved42[2];
-/** Offset 0x195A - Enable SATA Port DmVal
+/** Offset 0x195E - Enable SATA Port DmVal
DEVSLP Idle Timeout (DITO), Default is 625.
**/
UINT16 SataPortsDitoVal[8];
-/** Offset 0x196A - Enable SATA Port ZpOdd
+/** Offset 0x196E - Enable SATA Port ZpOdd
Support zero power ODD.
**/
UINT8 SataPortsZpOdd[8];
-/** Offset 0x1972 - PCH Sata Rst Raid Alternate Id
+/** Offset 0x1976 - PCH Sata Rst Raid Alternate Id
Enable RAID Alternate ID.
$EN_DIS
**/
UINT8 SataRstRaidDeviceId;
-/** Offset 0x1973 - PCH Sata Rst Pcie Storage Remap enable
+/** Offset 0x1977 - PCH Sata Rst Pcie Storage Remap enable
Enable Intel RST for PCIe Storage remapping.
**/
UINT8 SataRstPcieEnable[3];
-/** Offset 0x1976 - PCH Sata Rst Pcie Storage Port
+/** Offset 0x197A - PCH Sata Rst Pcie Storage Port
Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, 0 = autodetect).
**/
UINT8 SataRstPcieStoragePort[3];
-/** Offset 0x1979 - PCH Sata Rst Pcie Device Reset Delay
+/** Offset 0x197D - PCH Sata Rst Pcie Device Reset Delay
PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
**/
UINT8 SataRstPcieDeviceResetDelay[3];
-/** Offset 0x197C - UFS enable/disable
- PCIe Storage Device Reset Delay in milliseconds. Default value is 100ms
+/** Offset 0x1980 - UFS enable/disable
+ Enable/Disable UFS controller, One byte for each Controller - (1,0) to enable controller
+ 0 and (0,1) to enable controller 1
$EN_DIS
**/
UINT8 UfsEnable[2];
-/** Offset 0x197E - Reserved
+/** Offset 0x1982 - Reserved
**/
- UINT8 Reserved42[2];
+ UINT8 Reserved43[2];
-/** Offset 0x1980 - IEH Mode
+/** Offset 0x1984 - IEH Mode
Integrated Error Handler Mode, 0: Bypass, 1: Enable
0: Bypass, 1:Enable
**/
UINT8 IehMode;
-/** Offset 0x1981 - Reserved
+/** Offset 0x1985 - Reserved
**/
- UINT8 Reserved43[11];
+ UINT8 Reserved44[11];
-/** Offset 0x198C - PCH Thermal Throttling Custimized T0Level Value
+/** Offset 0x1990 - PCH Thermal Throttling Custimized T0Level Value
Custimized T0Level value.
**/
UINT16 PchT0Level;
-/** Offset 0x198E - PCH Thermal Throttling Custimized T1Level Value
+/** Offset 0x1992 - PCH Thermal Throttling Custimized T1Level Value
Custimized T1Level value.
**/
UINT16 PchT1Level;
-/** Offset 0x1990 - PCH Thermal Throttling Custimized T2Level Value
+/** Offset 0x1994 - PCH Thermal Throttling Custimized T2Level Value
Custimized T2Level value.
**/
UINT16 PchT2Level;
-/** Offset 0x1992 - Enable PCH Thermal Throttle
+/** Offset 0x1996 - Enable PCH Thermal Throttle
Enable thermal throttle function.
$EN_DIS
**/
UINT8 PchTTEnable;
-/** Offset 0x1993 - PCH PMSync State 13
+/** Offset 0x1997 - PCH PMSync State 13
When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13 will force
at least T2 state.
$EN_DIS
**/
UINT8 PchTTState13Enable;
-/** Offset 0x1994 - PCH Thermal Throttle Lock
+/** Offset 0x1998 - PCH Thermal Throttle Lock
Thermal Throttle Lock.
$EN_DIS
**/
UINT8 PchTTLock;
-/** Offset 0x1995 - Reserved
+/** Offset 0x1999 - Reserved
**/
- UINT8 Reserved44[9];
+ UINT8 Reserved45[9];
-/** Offset 0x199E - DMI Thermal Sensor Autonomous Width Enable
+/** Offset 0x19A2 - DMI Thermal Sensor Autonomous Width Enable
DMI Thermal Sensor Autonomous Width Enable.
$EN_DIS
**/
UINT8 PchDmiTsawEn;
-/** Offset 0x199F - DMI Thermal Sensor Suggested Setting
+/** Offset 0x19A3 - DMI Thermal Sensor Suggested Setting
DMT thermal sensor suggested representative values.
$EN_DIS
**/
UINT8 DmiSuggestedSetting;
-/** Offset 0x19A0 - Thermal Sensor 0 Target Width
+/** Offset 0x19A4 - Thermal Sensor 0 Target Width
Thermal Sensor 0 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS0TW;
-/** Offset 0x19A1 - Thermal Sensor 1 Target Width
+/** Offset 0x19A5 - Thermal Sensor 1 Target Width
Thermal Sensor 1 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS1TW;
-/** Offset 0x19A2 - Thermal Sensor 2 Target Width
+/** Offset 0x19A6 - Thermal Sensor 2 Target Width
Thermal Sensor 2 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS2TW;
-/** Offset 0x19A3 - Thermal Sensor 3 Target Width
+/** Offset 0x19A7 - Thermal Sensor 3 Target Width
Thermal Sensor 3 Target Width.
0:x1, 1:x2, 2:x4, 3:x8, 4:x16
**/
UINT8 DmiTS3TW;
-/** Offset 0x19A4 - Port 0 T1 Multipler
+/** Offset 0x19A8 - Port 0 T1 Multipler
Port 0 T1 Multipler.
**/
UINT8 SataP0T1M;
-/** Offset 0x19A5 - Port 0 T2 Multipler
+/** Offset 0x19A9 - Port 0 T2 Multipler
Port 0 T2 Multipler.
**/
UINT8 SataP0T2M;
-/** Offset 0x19A6 - Port 0 T3 Multipler
+/** Offset 0x19AA - Port 0 T3 Multipler
Port 0 T3 Multipler.
**/
UINT8 SataP0T3M;
-/** Offset 0x19A7 - Port 0 Tdispatch
+/** Offset 0x19AB - Port 0 Tdispatch
Port 0 Tdispatch.
**/
UINT8 SataP0TDisp;
-/** Offset 0x19A8 - Port 1 T1 Multipler
+/** Offset 0x19AC - Port 1 T1 Multipler
Port 1 T1 Multipler.
**/
UINT8 SataP1T1M;
-/** Offset 0x19A9 - Port 1 T2 Multipler
+/** Offset 0x19AD - Port 1 T2 Multipler
Port 1 T2 Multipler.
**/
UINT8 SataP1T2M;
-/** Offset 0x19AA - Port 1 T3 Multipler
+/** Offset 0x19AE - Port 1 T3 Multipler
Port 1 T3 Multipler.
**/
UINT8 SataP1T3M;
-/** Offset 0x19AB - Port 1 Tdispatch
+/** Offset 0x19AF - Port 1 Tdispatch
Port 1 Tdispatch.
**/
UINT8 SataP1TDisp;
-/** Offset 0x19AC - Port 0 Tinactive
+/** Offset 0x19B0 - Port 0 Tinactive
Port 0 Tinactive.
**/
UINT8 SataP0Tinact;
-/** Offset 0x19AD - Port 0 Alternate Fast Init Tdispatch
+/** Offset 0x19B1 - Port 0 Alternate Fast Init Tdispatch
Port 0 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP0TDispFinit;
-/** Offset 0x19AE - Port 1 Tinactive
+/** Offset 0x19B2 - Port 1 Tinactive
Port 1 Tinactive.
**/
UINT8 SataP1Tinact;
-/** Offset 0x19AF - Port 1 Alternate Fast Init Tdispatch
+/** Offset 0x19B3 - Port 1 Alternate Fast Init Tdispatch
Port 1 Alternate Fast Init Tdispatch.
$EN_DIS
**/
UINT8 SataP1TDispFinit;
-/** Offset 0x19B0 - Sata Thermal Throttling Suggested Setting
+/** Offset 0x19B4 - Sata Thermal Throttling Suggested Setting
Sata Thermal Throttling Suggested Setting.
$EN_DIS
**/
UINT8 SataThermalSuggestedSetting;
-/** Offset 0x19B1 - Reserved
+/** Offset 0x19B5 - Reserved
**/
- UINT8 Reserved45;
+ UINT8 Reserved46;
-/** Offset 0x19B2 - Thermal Device Temperature
+/** Offset 0x19B6 - Thermal Device Temperature
Decides the temperature.
**/
UINT16 PchTemperatureHotLevel;
-/** Offset 0x19B4 - USB2 Port Over Current Pin
+/** Offset 0x19B8 - USB2 Port Over Current Pin
Describe the specific over current pin number of USB 2.0 Port N.
**/
UINT8 Usb2OverCurrentPin[16];
-/** Offset 0x19C4 - USB3 Port Over Current Pin
+/** Offset 0x19C8 - USB3 Port Over Current Pin
Describe the specific over current pin number of USB 3.0 Port N.
**/
UINT8 Usb3OverCurrentPin[10];
-/** Offset 0x19CE - Enable xHCI LTR override
+/** Offset 0x19D2 - Enable xHCI LTR override
Enables override of recommended LTR values for xHCI
$EN_DIS
**/
UINT8 PchUsbLtrOverrideEnable;
-/** Offset 0x19CF - Reserved
+/** Offset 0x19D3 - Reserved
**/
- UINT8 Reserved46;
+ UINT8 Reserved47;
-/** Offset 0x19D0 - xHCI High Idle Time LTR override
+/** Offset 0x19D4 - xHCI High Idle Time LTR override
Value used for overriding LTR recommendation for xHCI High Idle Time LTR setting
**/
UINT32 PchUsbLtrHighIdleTimeOverride;
-/** Offset 0x19D4 - xHCI Medium Idle Time LTR override
+/** Offset 0x19D8 - xHCI Medium Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Medium Idle Time LTR setting
**/
UINT32 PchUsbLtrMediumIdleTimeOverride;
-/** Offset 0x19D8 - xHCI Low Idle Time LTR override
+/** Offset 0x19DC - xHCI Low Idle Time LTR override
Value used for overriding LTR recommendation for xHCI Low Idle Time LTR setting
**/
UINT32 PchUsbLtrLowIdleTimeOverride;
-/** Offset 0x19DC - Enable 8254 Static Clock Gating
+/** Offset 0x19E0 - Enable 8254 Static Clock Gating
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
legacy OS using 8254 timer. Also enable this while S0ix is enabled.
@@ -2057,7 +2062,7 @@ typedef struct {
**/
UINT8 Enable8254ClockGating;
-/** Offset 0x19DD - Enable 8254 Static Clock Gating On S3
+/** Offset 0x19E1 - Enable 8254 Static Clock Gating On S3
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
avoids the SMI requirement for the programming.
@@ -2065,7 +2070,7 @@ typedef struct {
**/
UINT8 Enable8254ClockGatingOnS3;
-/** Offset 0x19DE - Enable TCO timer.
+/** Offset 0x19E2 - Enable TCO timer.
When FALSE, it disables PCH ACPI timer, and stops TCO timer. NOTE: This will have
huge power impact when it's enabled. If TCO timer is disabled, uCode ACPI timer
emulation must be enabled, and WDAT table must not be exposed to the OS.
@@ -2073,102 +2078,102 @@ typedef struct {
**/
UINT8 EnableTcoTimer;
-/** Offset 0x19DF - Reserved
+/** Offset 0x19E3 - Reserved
**/
- UINT8 Reserved47;
+ UINT8 Reserved48[5];
-/** Offset 0x19E0 - BgpdtHash[4]
+/** Offset 0x19E8 - BgpdtHash[4]
BgpdtHash values
**/
UINT64 BgpdtHash[4];
-/** Offset 0x1A00 - BiosGuardAttr
+/** Offset 0x1A08 - BiosGuardAttr
BiosGuardAttr default values
**/
UINT32 BiosGuardAttr;
-/** Offset 0x1A04 - Reserved
+/** Offset 0x1A0C - Reserved
**/
- UINT8 Reserved48[4];
+ UINT8 Reserved49[4];
-/** Offset 0x1A08 - BiosGuardModulePtr
+/** Offset 0x1A10 - BiosGuardModulePtr
BiosGuardModulePtr default values
**/
UINT64 BiosGuardModulePtr;
-/** Offset 0x1A10 - SendEcCmd
+/** Offset 0x1A18 - SendEcCmd
SendEcCmd function pointer. \n
@code typedef EFI_STATUS (EFIAPI *PLATFORM_SEND_EC_COMMAND) (IN EC_COMMAND_TYPE
EcCmdType, IN UINT8 EcCmd, IN UINT8 SendData, IN OUT UINT8 *ReceiveData); @endcode
**/
UINT64 SendEcCmd;
-/** Offset 0x1A18 - EcCmdProvisionEav
+/** Offset 0x1A20 - EcCmdProvisionEav
Ephemeral Authorization Value default values. Provisions an ephemeral shared secret to the EC
**/
UINT8 EcCmdProvisionEav;
-/** Offset 0x1A19 - EcCmdLock
+/** Offset 0x1A21 - EcCmdLock
EcCmdLock default values. Locks Ephemeral Authorization Value sent previously
**/
UINT8 EcCmdLock;
-/** Offset 0x1A1A - Reserved
+/** Offset 0x1A22 - Reserved
**/
- UINT8 Reserved49[22];
+ UINT8 Reserved50[22];
-/** Offset 0x1A30 - Skip Ssid Programming.
+/** Offset 0x1A38 - Skip Ssid Programming.
When set to TRUE, silicon code will not do any SSID programming and platform code
needs to handle that by itself properly.
$EN_DIS
**/
UINT8 SiSkipSsidProgramming;
-/** Offset 0x1A31 - Reserved
+/** Offset 0x1A39 - Reserved
**/
- UINT8 Reserved50;
+ UINT8 Reserved51;
-/** Offset 0x1A32 - Change Default SVID
+/** Offset 0x1A3A - Change Default SVID
Change the default SVID used in FSP to programming internal devices. This is only
valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiCustomizedSvid;
-/** Offset 0x1A34 - Change Default SSID
+/** Offset 0x1A3C - Change Default SSID
Change the default SSID used in FSP to programming internal devices. This is only
valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiCustomizedSsid;
-/** Offset 0x1A36 - Reserved
+/** Offset 0x1A3E - Reserved
**/
- UINT8 Reserved51[2];
+ UINT8 Reserved52[2];
-/** Offset 0x1A38 - SVID SDID table Poniter.
+/** Offset 0x1A40 - SVID SDID table Poniter.
The address of the table of SVID SDID to customize each SVID SDID entry. This is
only valid when SkipSsidProgramming is FALSE.
**/
UINT32 SiSsidTablePtr;
-/** Offset 0x1A3C - Number of ssid table.
+/** Offset 0x1A44 - Number of ssid table.
SiNumberOfSsidTableEntry should match the table entries created in SiSsidTablePtr.
This is only valid when SkipSsidProgramming is FALSE.
**/
UINT16 SiNumberOfSsidTableEntry;
-/** Offset 0x1A3E - USB2 Port Reset Message Enable
+/** Offset 0x1A46 - USB2 Port Reset Message Enable
0: Disable USB2 Port Reset Message; 1: Enable USB2 Port Reset Message; This must
be enable for USB2 Port those are paired with CPU XHCI Port
**/
UINT8 PortResetMessageEnable[16];
-/** Offset 0x1A4E - SATA RST Interrupt Mode
+/** Offset 0x1A56 - SATA RST Interrupt Mode
Allowes to choose which interrupts will be implemented by SATA controller in RAID mode.
0:Msix, 1:Msi, 2:Legacy
**/
UINT8 SataRstInterrupt;
-/** Offset 0x1A4F - Enable PS_ON.
+/** Offset 0x1A57 - Enable PS_ON.
PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power
target that will be required by the California Energy Commission (CEC). When FALSE,
PS_ON is to be disabled.
@@ -2176,114 +2181,114 @@ typedef struct {
**/
UINT8 PsOnEnable;
-/** Offset 0x1A50 - Pmc Cpu C10 Gate Pin Enable
+/** Offset 0x1A58 - Pmc Cpu C10 Gate Pin Enable
Enable/Disable platform support for CPU_C10_GATE# pin to control gating of CPU VccIO
and VccSTG rails instead of SLP_S0# pin.
$EN_DIS
**/
UINT8 PmcCpuC10GatePinEnable;
-/** Offset 0x1A51 - Pch Dmi Aspm Ctrl
+/** Offset 0x1A59 - Pch Dmi Aspm Ctrl
ASPM configuration on the PCH side of the DMI/OPI Link. Default is <b>PchPcieAspmAutoConfig</b>
0:Disabled, 1:L0s, 2:L1, 3:L0sL1, 4:Auto
**/
UINT8 PchDmiAspmCtrl;
-/** Offset 0x1A52 - PchDmiCwbEnable
+/** Offset 0x1A5A - PchDmiCwbEnable
Central Write Buffer feature configurable and enabled by default
$EN_DIS
**/
UINT8 PchDmiCwbEnable;
-/** Offset 0x1A53 - OS IDLE Mode Enable
+/** Offset 0x1A5B - OS IDLE Mode Enable
Enable/Disable OS Idle Mode
$EN_DIS
**/
UINT8 PmcOsIdleEnable;
-/** Offset 0x1A54 - S0ix Auto-Demotion
+/** Offset 0x1A5C - S0ix Auto-Demotion
Enable/Disable the Low Power Mode Auto-Demotion Host Control feature.
$EN_DIS
**/
UINT8 PchS0ixAutoDemotion;
-/** Offset 0x1A55 - Latch Events C10 Exit
+/** Offset 0x1A5D - Latch Events C10 Exit
When this bit is set to 1, SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are
captured on C10 exit (instead of C10 entry which is default)
$EN_DIS
**/
UINT8 PchPmLatchEventsC10Exit;
-/** Offset 0x1A56 - Reserved
+/** Offset 0x1A5E - Reserved
**/
- UINT8 Reserved52[99];
+ UINT8 Reserved53[99];
-/** Offset 0x1AB9 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
+/** Offset 0x1AC1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 3, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTranEnable[10];
-/** Offset 0x1AC3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
+/** Offset 0x1ACB - USB 3.0 TX Output Unique Transition Bit Scale for rate 3
USB 3.0 TX Output Unique Transition Bit Scale for rate 3, HSIO_TX_DWORD9[6:0], <b>Default
= 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate3UniqTran[10];
-/** Offset 0x1ACD - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
+/** Offset 0x1AD5 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 2, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTranEnable[10];
-/** Offset 0x1AD7 - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
+/** Offset 0x1ADF - USB 3.0 TX Output Unique Transition Bit Scale for rate 2
USB 3.0 TX Output Unique Transition Bit Scale for rate 2, HSIO_TX_DWORD9[14:8],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate2UniqTran[10];
-/** Offset 0x1AE1 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
+/** Offset 0x1AE9 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 1, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTranEnable[10];
-/** Offset 0x1AEB - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
+/** Offset 0x1AF3 - USB 3.0 TX Output Unique Transition Bit Scale for rate 1
USB 3.0 TX Output Unique Transition Bit Scale for rate 1, HSIO_TX_DWORD9[22:16],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate1UniqTran[10];
-/** Offset 0x1AF5 - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
+/** Offset 0x1AFD - Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0
Enable the write to USB 3.0 TX Output Unique Transition Bit Mode for rate 0, Each
value in array can be between 0-1. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTranEnable[10];
-/** Offset 0x1AFF - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
+/** Offset 0x1B07 - USB 3.0 TX Output Unique Transition Bit Scale for rate 0
USB 3.0 TX Output Unique Transition Bit Scale for rate 0, HSIO_TX_DWORD9[30:24],
<b>Default = 4Ch</b>. One byte for each port.
**/
UINT8 Usb3HsioTxRate0UniqTran[10];
-/** Offset 0x1B09 - Skip PAM regsiter lock
+/** Offset 0x1B11 - Skip PAM regsiter lock
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
$EN_DIS
**/
UINT8 SkipPamLock;
-/** Offset 0x1B0A - Enable/Disable IGFX RenderStandby
+/** Offset 0x1B12 - Enable/Disable IGFX RenderStandby
Enable(Default): Enable IGFX RenderStandby, Disable: Disable IGFX RenderStandby
$EN_DIS
**/
UINT8 RenderStandby;
-/** Offset 0x1B0B - Reserved
+/** Offset 0x1B13 - Reserved
**/
- UINT8 Reserved53;
+ UINT8 Reserved54;
-/** Offset 0x1B0C - GT Frequency Limit
+/** Offset 0x1B14 - GT Frequency Limit
0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz,
7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD:
650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz,
@@ -2297,51 +2302,51 @@ typedef struct {
**/
UINT8 GtFreqMax;
-/** Offset 0x1B0D - Disable Turbo GT
+/** Offset 0x1B15 - Disable Turbo GT
0=Disable: GT frequency is not limited, 1=Enable: Disables Turbo GT frequency
$EN_DIS
**/
UINT8 DisableTurboGt;
-/** Offset 0x1B0E - Reserved
+/** Offset 0x1B16 - Reserved
**/
- UINT8 Reserved54[2];
+ UINT8 Reserved55[2];
-/** Offset 0x1B10 - Enable TSN Multi-VC
+/** Offset 0x1B18 - Enable TSN Multi-VC
Enable/disable Multi Virtual Channels(VC) in TSN.
$EN_DIS
**/
UINT8 PchTsnMultiVcEnable;
-/** Offset 0x1B11 - Reserved
+/** Offset 0x1B19 - Reserved
**/
- UINT8 Reserved55[3];
+ UINT8 Reserved56[3];
-/** Offset 0x1B14 - LogoPixelHeight Address
+/** Offset 0x1B1C - LogoPixelHeight Address
Address of LogoPixelHeight
**/
UINT32 LogoPixelHeight;
-/** Offset 0x1B18 - LogoPixelWidth Address
+/** Offset 0x1B20 - LogoPixelWidth Address
Address of LogoPixelWidth
**/
UINT32 LogoPixelWidth;
-/** Offset 0x1B1C - Reserved
+/** Offset 0x1B24 - Reserved
**/
- UINT8 Reserved56[45];
+ UINT8 Reserved57[45];
-/** Offset 0x1B49 - RSR feature
+/** Offset 0x1B51 - RSR feature
Enable or Disable RSR feature; 0: Disable; <b>1: Enable </b>
$EN_DIS
**/
UINT8 EnableRsr;
-/** Offset 0x1B4A - Reserved
+/** Offset 0x1B52 - Reserved
**/
- UINT8 Reserved57[4];
+ UINT8 Reserved58[4];
-/** Offset 0x1B4E - Enable or Disable HWP
+/** Offset 0x1B56 - Enable or Disable HWP
Enable/Disable Intel(R) Speed Shift Technology support. Enabling will expose the
CPPC v2 interface to allow for hardware controlled P-states. 0: Disable; <b>1:
Enable;</b>
@@ -2349,7 +2354,7 @@ typedef struct {
**/
UINT8 Hwp;
-/** Offset 0x1B4F - Package Long duration turbo mode time
+/** Offset 0x1B57 - Package Long duration turbo mode time
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained. Valid values(Unit
@@ -2358,14 +2363,14 @@ typedef struct {
**/
UINT8 PowerLimit1Time;
-/** Offset 0x1B50 - Short Duration Turbo Mode
+/** Offset 0x1B58 - Short Duration Turbo Mode
Enable/Disable Power Limit 2 override. If this option is disabled, BIOS will program
the default values for Power Limit 2. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PowerLimit2;
-/** Offset 0x1B51 - Turbo settings Lock
+/** Offset 0x1B59 - Turbo settings Lock
Enable/Disable locking of Package Power Limit settings. When enabled, PACKAGE_POWER_LIMIT
MSR will be locked and a reset will be required to unlock the register. <b>0: Disable;
</b> 1: Enable
@@ -2373,7 +2378,7 @@ typedef struct {
**/
UINT8 TurboPowerLimitLock;
-/** Offset 0x1B52 - Package PL3 time window
+/** Offset 0x1B5A - Package PL3 time window
Power Limit 3 Time Window value in Milli seconds. Indicates the time window over
which Power Limit 3 value should be maintained. If the value is 0, BIOS leaves
the hardware default value. Valid value: <b>0</b>, 3-8, 10, 12, 14, 16, 20, 24,
@@ -2381,108 +2386,108 @@ typedef struct {
**/
UINT8 PowerLimit3Time;
-/** Offset 0x1B53 - Package PL3 Duty Cycle
+/** Offset 0x1B5B - Package PL3 Duty Cycle
Specify the duty cycle in percentage that the CPU is required to maintain over the
configured time window. Range is 0-100.
**/
UINT8 PowerLimit3DutyCycle;
-/** Offset 0x1B54 - Package PL3 Lock
+/** Offset 0x1B5C - Package PL3 Lock
Power Limit 3 Lock. When enabled PL3 configurations are locked during OS. When disabled
PL3 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit3Lock;
-/** Offset 0x1B55 - Package PL4 Lock
+/** Offset 0x1B5D - Package PL4 Lock
Power Limit 4 Lock. When enabled PL4 configurations are locked during OS. When disabled
PL4 configuration can be changed during OS. <b>0: Disable</b> ; 1:Enable
$EN_DIS
**/
UINT8 PowerLimit4Lock;
-/** Offset 0x1B56 - TCC Activation Offset
+/** Offset 0x1B5E - TCC Activation Offset
TCC Activation Offset. Offset from factory set TCC activation temperature at which
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
Temperature, in volts. <b>Default = 0h</b>.
**/
UINT8 TccActivationOffset;
-/** Offset 0x1B57 - Tcc Offset Clamp Enable/Disable
+/** Offset 0x1B5F - Tcc Offset Clamp Enable/Disable
Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU to throttle
below P1. <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetClamp;
-/** Offset 0x1B58 - Tcc Offset Lock
+/** Offset 0x1B60 - Tcc Offset Lock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
target; <b>0: Disabled</b>; 1: Enabled.
$EN_DIS
**/
UINT8 TccOffsetLock;
-/** Offset 0x1B59 - Custom Ratio State Entries
+/** Offset 0x1B61 - Custom Ratio State Entries
The number of custom ratio state entries, ranges from 0 to 40 for a valid custom
ratio table. Sets the number of custom P-states. At least 2 states must be present
**/
UINT8 NumberOfEntries;
-/** Offset 0x1B5A - Custom Short term Power Limit time window
+/** Offset 0x1B62 - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom1PowerLimit1Time;
-/** Offset 0x1B5B - Custom Turbo Activation Ratio
+/** Offset 0x1B63 - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom1TurboActivationRatio;
-/** Offset 0x1B5C - Custom Config Tdp Control
+/** Offset 0x1B64 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom1ConfigTdpControl;
-/** Offset 0x1B5D - Custom Short term Power Limit time window
+/** Offset 0x1B65 - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom2PowerLimit1Time;
-/** Offset 0x1B5E - Custom Turbo Activation Ratio
+/** Offset 0x1B66 - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom2TurboActivationRatio;
-/** Offset 0x1B5F - Custom Config Tdp Control
+/** Offset 0x1B67 - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom2ConfigTdpControl;
-/** Offset 0x1B60 - Custom Short term Power Limit time window
+/** Offset 0x1B68 - Custom Short term Power Limit time window
Power Limit 1 Time Window value in seconds. The value may vary from 0 to 128. 0
= default value (28 sec for Mobile and 8 sec for Desktop). Defines time window
which Processor Base Power (TDP) value should be maintained.
**/
UINT8 Custom3PowerLimit1Time;
-/** Offset 0x1B61 - Custom Turbo Activation Ratio
+/** Offset 0x1B69 - Custom Turbo Activation Ratio
Custom value for Turbo Activation Ratio. Needs to be configured with valid values
from LFM to Max Turbo. 0 means don't use custom value. Valid Range 0 to 255
**/
UINT8 Custom3TurboActivationRatio;
-/** Offset 0x1B62 - Custom Config Tdp Control
+/** Offset 0x1B6A - Custom Config Tdp Control
Config Tdp Control (0/1/2) value for custom cTDP level 1. Valid Range is 0 to 2
**/
UINT8 Custom3ConfigTdpControl;
-/** Offset 0x1B63 - ConfigTdp mode settings Lock
+/** Offset 0x1B6B - ConfigTdp mode settings Lock
Configurable Processor Base Power (cTDP) Mode Lock sets the Lock bits on TURBO_ACTIVATION_RATIO
and CONFIG_TDP_CONTROL. Note: When CTDP Lock is enabled Custom ConfigTDP Count
will be forced to 1 and Custom ConfigTDP Boot Index will be forced to 0. <b>0:
@@ -2491,7 +2496,7 @@ typedef struct {
**/
UINT8 ConfigTdpLock;
-/** Offset 0x1B64 - Load Configurable TDP SSDT
+/** Offset 0x1B6C - Load Configurable TDP SSDT
Enables Configurable Processor Base Power (cTDP) control via runtime ACPI BIOS methods.
This 'BIOS only' feature does not require EC or driver support. <b>0: Disable</b>;
1: Enable.
@@ -2499,7 +2504,7 @@ typedef struct {
**/
UINT8 ConfigTdpBios;
-/** Offset 0x1B65 - PL1 Enable value
+/** Offset 0x1B6D - PL1 Enable value
Enable/Disable Platform Power Limit 1 programming. If this option is enabled, it
activates the PL1 value to be used by the processor to limit the average power
of given time window. <b>0: Disable</b>; 1: Enable.
@@ -2507,7 +2512,7 @@ typedef struct {
**/
UINT8 PsysPowerLimit1;
-/** Offset 0x1B66 - PL1 timewindow
+/** Offset 0x1B6E - PL1 timewindow
Platform Power Limit 1 Time Window value in seconds. The value may vary from 0 to
128. 0 = default values. Indicates the time window over which Platform Processor
Base Power (TDP) value should be maintained. Valid values(Unit in seconds) 0 to
@@ -2515,7 +2520,7 @@ typedef struct {
**/
UINT8 PsysPowerLimit1Time;
-/** Offset 0x1B67 - PL2 Enable Value
+/** Offset 0x1B6F - PL2 Enable Value
Enable/Disable Platform Power Limit 2 programming. If this option is disabled, BIOS
will program the default values for Platform Power Limit 2. <b>0: Disable</b>;
1: Enable.
@@ -2523,57 +2528,57 @@ typedef struct {
**/
UINT8 PsysPowerLimit2;
-/** Offset 0x1B68 - Enable or Disable MLC Streamer Prefetcher
+/** Offset 0x1B70 - Enable or Disable MLC Streamer Prefetcher
Enable or Disable MLC Streamer Prefetcher; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MlcStreamerPrefetcher;
-/** Offset 0x1B69 - Enable or Disable MLC Spatial Prefetcher
+/** Offset 0x1B71 - Enable or Disable MLC Spatial Prefetcher
Enable or Disable MLC Spatial Prefetcher; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 MlcSpatialPrefetcher;
-/** Offset 0x1B6A - Enable or Disable Monitor /MWAIT instructions
+/** Offset 0x1B72 - Enable or Disable Monitor /MWAIT instructions
Enable/Disable MonitorMWait, if Disable MonitorMwait, the AP threads Idle Manner
should not set in MWAIT Loop. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MonitorMwaitEnable;
-/** Offset 0x1B6B - Enable or Disable initialization of machine check registers
+/** Offset 0x1B73 - Enable or Disable initialization of machine check registers
Enable or Disable initialization of machine check registers; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 MachineCheckEnable;
-/** Offset 0x1B6C - AP Idle Manner of waiting for SIPI
+/** Offset 0x1B74 - AP Idle Manner of waiting for SIPI
AP threads Idle Manner for waiting signal to run. 1: HALT loop; <b>2: MWAIT loop</b>;
3: RUN loop.
1: HALT loop, 2: MWAIT loop, 3: RUN loop
**/
UINT8 ApIdleManner;
-/** Offset 0x1B6D - Control on Processor Trace output scheme
+/** Offset 0x1B75 - Control on Processor Trace output scheme
Control on Processor Trace output scheme; <b>0: Single Range Output</b>; 1: ToPA Output.
0: Single Range Output, 1: ToPA Output
**/
UINT8 ProcessorTraceOutputScheme;
-/** Offset 0x1B6E - Enable or Disable Processor Trace feature
+/** Offset 0x1B76 - Enable or Disable Processor Trace feature
Enable or Disable Processor Trace feature; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcessorTraceEnable;
-/** Offset 0x1B6F - Enable or Disable Intel SpeedStep Technology
+/** Offset 0x1B77 - Enable or Disable Intel SpeedStep Technology
Allows more than two frequency ranges to be supported. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Eist;
-/** Offset 0x1B70 - Enable or Disable Energy Efficient P-state
+/** Offset 0x1B78 - Enable or Disable Energy Efficient P-state
Enable/Disable Energy Efficient P-state feature. When set to 0, will disable access
to ENERGY_PERFORMANCE_BIAS MSR and CPUID Function will read 0 indicating no support
for Energy Efficient policy setting. When set to 1 will enable access to ENERGY_PERFORMANCE_BIAS
@@ -2583,7 +2588,7 @@ typedef struct {
**/
UINT8 EnergyEfficientPState;
-/** Offset 0x1B71 - Enable or Disable Energy Efficient Turbo
+/** Offset 0x1B79 - Enable or Disable Energy Efficient Turbo
Enable/Disable Energy Efficient Turbo Feature. This feature will opportunistically
lower the turbo frequency to increase efficiency. Recommended only to disable in
overclocking situations where turbo frequency must remain constant. Otherwise,
@@ -2592,100 +2597,100 @@ typedef struct {
**/
UINT8 EnergyEfficientTurbo;
-/** Offset 0x1B72 - Enable or Disable T states
+/** Offset 0x1B7A - Enable or Disable T states
Enable or Disable T states; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 TStates;
-/** Offset 0x1B73 - Enable or Disable Bi-Directional PROCHOT#
+/** Offset 0x1B7B - Enable or Disable Bi-Directional PROCHOT#
Enable or Disable Bi-Directional PROCHOT#; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 BiProcHot;
-/** Offset 0x1B74 - Enable or Disable PROCHOT# signal being driven externally
+/** Offset 0x1B7C - Enable or Disable PROCHOT# signal being driven externally
Enable or Disable PROCHOT# signal being driven externally; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 DisableProcHotOut;
-/** Offset 0x1B75 - Enable or Disable PROCHOT# Response
+/** Offset 0x1B7D - Enable or Disable PROCHOT# Response
Enable or Disable PROCHOT# Response; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 ProcHotResponse;
-/** Offset 0x1B76 - Enable or Disable VR Thermal Alert
+/** Offset 0x1B7E - Enable or Disable VR Thermal Alert
Enable or Disable VR Thermal Alert; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 DisableVrThermalAlert;
-/** Offset 0x1B77 - Enable or Disable Thermal Reporting
+/** Offset 0x1B7F - Enable or Disable Thermal Reporting
Enable or Disable Thermal Reporting through ACPI tables; 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 EnableAllThermalFunctions;
-/** Offset 0x1B78 - Enable or Disable Thermal Monitor
+/** Offset 0x1B80 - Enable or Disable Thermal Monitor
Enable or Disable Thermal Monitor; 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 ThermalMonitor;
-/** Offset 0x1B79 - Enable or Disable CPU power states (C-states)
+/** Offset 0x1B81 - Enable or Disable CPU power states (C-states)
Enable/Disable CPU Power Management. Allows CPU to go to C states when it's not
100% utilized. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 Cx;
-/** Offset 0x1B7A - Configure C-State Configuration Lock
+/** Offset 0x1B82 - Configure C-State Configuration Lock
Configure MSR to CFG Lock bit. 0: Disable; <b>1: Enable</b>.
$EN_DIS
**/
UINT8 PmgCstCfgCtrlLock;
-/** Offset 0x1B7B - Enable or Disable Enhanced C-states
+/** Offset 0x1B83 - Enable or Disable Enhanced C-states
Enable/Disable C1E. When enabled, CPU will switch to minimum speed when all cores
enter C-State. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1e;
-/** Offset 0x1B7C - Enable or Disable Package Cstate Demotion
+/** Offset 0x1B84 - Enable or Disable Package Cstate Demotion
Enable or Disable Package C-State Demotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateDemotion;
-/** Offset 0x1B7D - Enable or Disable Package Cstate UnDemotion
+/** Offset 0x1B85 - Enable or Disable Package Cstate UnDemotion
Enable or Disable Package C-State Un-Demotion. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 PkgCStateUnDemotion;
-/** Offset 0x1B7E - Enable or Disable CState-Pre wake
+/** Offset 0x1B86 - Enable or Disable CState-Pre wake
Disable - to disable the Cstate Pre-Wake. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 CStatePreWake;
-/** Offset 0x1B7F - Enable or Disable TimedMwait Support.
+/** Offset 0x1B87 - Enable or Disable TimedMwait Support.
Enable or Disable TimedMwait Support. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 TimedMwait;
-/** Offset 0x1B80 - Enable or Disable IO to MWAIT redirection
+/** Offset 0x1B88 - Enable or Disable IO to MWAIT redirection
When set, will map IO_read instructions sent to IO registers PMG_IO_BASE_ADDRBASE+offset
to MWAIT(offset). <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 CstCfgCtrIoMwaitRedirection;
-/** Offset 0x1B81 - Set the Max Pkg Cstate
+/** Offset 0x1B89 - Set the Max Pkg Cstate
Maximum Package C State Limit Setting. Cpu Default: Leaves to Factory default value.
Auto: Initializes to deepest available Package C State Limit. Valid values 0 -
C0/C1, 1 - C2, 2 - C3, 3 - C6, 4 - C7, 5 - C7S, 6 - C8, 7 - C9, 8 - C10, 254 -
@@ -2693,38 +2698,38 @@ typedef struct {
**/
UINT8 PkgCStateLimit;
-/** Offset 0x1B82 - Interrupt Redirection Mode Select
+/** Offset 0x1B8A - Interrupt Redirection Mode Select
Interrupt Redirection Mode Select for Logical Interrupts. 0: Fixed priority; 1:
Round robin; 2: Hash vector; 7: No change.
**/
UINT8 PpmIrmSetting;
-/** Offset 0x1B83 - Lock prochot configuration
+/** Offset 0x1B8B - Lock prochot configuration
Lock prochot configuration Enable/Disable; 0: Disable;<b> 1: Enable</b>
$EN_DIS
**/
UINT8 ProcHotLock;
-/** Offset 0x1B84 - Configuration for boot TDP selection
+/** Offset 0x1B8C - Configuration for boot TDP selection
Configurable Processor Base Power (cTDP) Mode as Nominal/Level1/Level2/Deactivate
TDP selection. Deactivate option will set MSR to Nominal and MMIO to Zero. <b>0:
TDP Nominal</b>; 1: TDP Down; 2: TDP Up;0xFF : Deactivate
**/
UINT8 ConfigTdpLevel;
-/** Offset 0x1B85 - Max P-State Ratio
+/** Offset 0x1B8D - Max P-State Ratio
Maximum P-state ratio to use in the custom P-state table. Valid Range 0 to 0x7F
**/
UINT8 MaxRatio;
-/** Offset 0x1B86 - P-state ratios for custom P-state table
+/** Offset 0x1B8E - P-state ratios for custom P-state table
P-state ratios for custom P-state table. NumberOfEntries has valid range between
0 to 40. For no. of P-States supported(NumberOfEntries) , StateRatio[NumberOfEntries]
are configurable. Valid Range of each entry is 0 to 0x7F
**/
UINT8 StateRatio[40];
-/** Offset 0x1BAE - P-state ratios for max 16 version of custom P-state table
+/** Offset 0x1BB6 - P-state ratios for max 16 version of custom P-state table
P-state ratios for max 16 version of custom P-state table. This table is used for
OS versions limited to a max of 16 P-States. If the first entry of this table is
0, or if Number of Entries is 16 or less, then this table will be ignored, and
@@ -2733,11 +2738,11 @@ typedef struct {
**/
UINT8 StateRatioMax16[16];
-/** Offset 0x1BBE - Reserved
+/** Offset 0x1BC6 - Reserved
**/
- UINT8 Reserved58[2];
+ UINT8 Reserved59[2];
-/** Offset 0x1BC0 - Package Long duration turbo mode power limit
+/** Offset 0x1BC8 - Package Long duration turbo mode power limit
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2747,7 +2752,7 @@ typedef struct {
**/
UINT32 PowerLimit1;
-/** Offset 0x1BC4 - Package Short duration turbo mode power limit
+/** Offset 0x1BCC - Package Short duration turbo mode power limit
Power Limit 2 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. If the value is 0, BIOS will program this value as 1.25*Processor
Base Power (TDP). Processor applies control policies such that the package power
@@ -2756,7 +2761,7 @@ typedef struct {
**/
UINT32 PowerLimit2Power;
-/** Offset 0x1BC8 - Package PL3 power limit
+/** Offset 0x1BD0 - Package PL3 power limit
Power Limit 3 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. XE SKU: Any value can be programmed. Overclocking SKU: Value
must be between Max and Min Power Limits. Other SKUs: This value must be between
@@ -2766,22 +2771,22 @@ typedef struct {
**/
UINT32 PowerLimit3;
-/** Offset 0x1BCC - Package PL4 power limit
+/** Offset 0x1BD4 - Package PL4 power limit
Power Limit 4 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. If the value is 0, BIOS leaves default value. Units are based
on POWER_MGMT_CONFIG.CustomPowerUnit. Valid Range 0 to 32767.
**/
UINT32 PowerLimit4;
-/** Offset 0x1BD0 - Reserved
+/** Offset 0x1BD8 - Reserved
**/
- UINT8 Reserved59[4];
+ UINT8 Reserved60[4];
-/** Offset 0x1BD4 - Tcc Offset Time Window for RATL
+/** Offset 0x1BDC - Tcc Offset Time Window for RATL
**/
UINT32 TccOffsetTimeWindowForRatl;
-/** Offset 0x1BD8 - Short term Power Limit value for custom cTDP level 1
+/** Offset 0x1BE0 - Short term Power Limit value for custom cTDP level 1
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2790,7 +2795,7 @@ typedef struct {
**/
UINT32 Custom1PowerLimit1;
-/** Offset 0x1BDC - Long term Power Limit value for custom cTDP level 1
+/** Offset 0x1BE4 - Long term Power Limit value for custom cTDP level 1
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -2798,7 +2803,7 @@ typedef struct {
**/
UINT32 Custom1PowerLimit2;
-/** Offset 0x1BE0 - Short term Power Limit value for custom cTDP level 2
+/** Offset 0x1BE8 - Short term Power Limit value for custom cTDP level 2
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2807,7 +2812,7 @@ typedef struct {
**/
UINT32 Custom2PowerLimit1;
-/** Offset 0x1BE4 - Long term Power Limit value for custom cTDP level 2
+/** Offset 0x1BEC - Long term Power Limit value for custom cTDP level 2
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -2815,7 +2820,7 @@ typedef struct {
**/
UINT32 Custom2PowerLimit2;
-/** Offset 0x1BE8 - Short term Power Limit value for custom cTDP level 3
+/** Offset 0x1BF0 - Short term Power Limit value for custom cTDP level 3
Power Limit 1 in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Overclocking SKU: Value must be between
Max and Min Power Limits. Other SKUs: This value must be between Min Power Limit
@@ -2824,7 +2829,7 @@ typedef struct {
**/
UINT32 Custom3PowerLimit1;
-/** Offset 0x1BEC - Long term Power Limit value for custom cTDP level 3
+/** Offset 0x1BF4 - Long term Power Limit value for custom cTDP level 3
Power Limit 2 value in Milli Watts. BIOS will round to the nearest 1/8W when programming.
Value set 120 = 15W. 0 = no custom override. Processor applies control policies
such that the package power does not exceed this limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.
@@ -2832,7 +2837,7 @@ typedef struct {
**/
UINT32 Custom3PowerLimit2;
-/** Offset 0x1BF0 - Platform PL1 power
+/** Offset 0x1BF8 - Platform PL1 power
Platform Power Limit 1 Power in Milli Watts. BIOS will round to the nearest 1/8W
when programming. Value set 120 = 15W. Any value can be programmed between Max
and Min Power Limits. This setting will act as the new PL1 value for the Package
@@ -2841,7 +2846,7 @@ typedef struct {
**/
UINT32 PsysPowerLimit1Power;
-/** Offset 0x1BF4 - Platform PL2 power
+/** Offset 0x1BFC - Platform PL2 power
Platform Power Limit 2 Power in Milli Watts. BIOS will round to the nearest 1/8W
when programming. Value set 120 = 15W. Any value can be programmed between Max
and Min Power Limits. This setting will act as the new PL2 value for the Package
@@ -2850,11 +2855,11 @@ typedef struct {
**/
UINT32 PsysPowerLimit2Power;
-/** Offset 0x1BF8 - Reserved
+/** Offset 0x1C00 - Reserved
**/
- UINT8 Reserved60;
+ UINT8 Reserved61;
-/** Offset 0x1BF9 - Race To Halt
+/** Offset 0x1C01 - Race To Halt
Enable/Disable Race To Halt feature. RTH will dynamically increase CPU frequency
in order to enter pkg C-State faster to reduce overall power. 0: Disable; <b>1:
Enable</b>
@@ -2862,66 +2867,66 @@ typedef struct {
**/
UINT8 RaceToHalt;
-/** Offset 0x1BFA - Reserved
+/** Offset 0x1C02 - Reserved
**/
- UINT8 Reserved61;
+ UINT8 Reserved62;
-/** Offset 0x1BFB - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
+/** Offset 0x1C03 - Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT
Set HW P-State Interrupts Enabled for for MISC_PWR_MGMT; <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 HwpInterruptControl;
-/** Offset 0x1BFC - Reserved
+/** Offset 0x1C04 - Reserved
**/
- UINT8 Reserved62[4];
+ UINT8 Reserved63[4];
-/** Offset 0x1C00 - Intel Turbo Boost Max Technology 3.0
+/** Offset 0x1C08 - Intel Turbo Boost Max Technology 3.0
Enable/Disable Intel(R) Turbo Boost Max Technology 3.0 support. Disabling will report
the maximum ratio of the slowest core in _CPC object. 0: Disabled; <b>1: Enabled</b>
$EN_DIS
**/
UINT8 EnableItbm;
-/** Offset 0x1C01 - Enable or Disable C1 Cstate Demotion
+/** Offset 0x1C09 - Enable or Disable C1 Cstate Demotion
Enable or Disable C1 Cstate Auto Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateAutoDemotion;
-/** Offset 0x1C02 - Enable or Disable C1 Cstate UnDemotion
+/** Offset 0x1C0A - Enable or Disable C1 Cstate UnDemotion
Enable or Disable C1 Cstate Un-Demotion. Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 C1StateUnDemotion;
-/** Offset 0x1C03 - Minimum Ring ratio limit override
+/** Offset 0x1C0B - Minimum Ring ratio limit override
Minimum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MinRingRatioLimit;
-/** Offset 0x1C04 - Maximum Ring ratio limit override
+/** Offset 0x1C0C - Maximum Ring ratio limit override
Maximum Ring ratio limit override. <b>0: Hardware defaults.</b> Range: 0 - Max turbo
ratio limit
**/
UINT8 MaxRingRatioLimit;
-/** Offset 0x1C05 - Enable or Disable Per Core P State OS control
+/** Offset 0x1C0D - Enable or Disable Per Core P State OS control
Enable/Disable Per Core P state OS control mode. When set, the highest core request
is used for all other core requests. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnablePerCorePState;
-/** Offset 0x1C06 - Enable or Disable HwP Autonomous Per Core P State OS control
+/** Offset 0x1C0E - Enable or Disable HwP Autonomous Per Core P State OS control
Disable Autonomous PCPS Autonomous will request the same value for all cores all
the time. 0: Disable; <b>1: Enable</b>
$EN_DIS
**/
UINT8 EnableHwpAutoPerCorePstate;
-/** Offset 0x1C07 - Enable or Disable HwP Autonomous EPP Grouping
+/** Offset 0x1C0F - Enable or Disable HwP Autonomous EPP Grouping
Enable EPP grouping Autonomous will request the same values for all cores with same
EPP. Disable EPP grouping autonomous will not necessarily request same values for
all cores with same EPP. <b> 0: Disable </b>; 1: Enable
@@ -2929,7 +2934,7 @@ typedef struct {
**/
UINT8 EnableHwpAutoEppGrouping;
-/** Offset 0x1C08 - Enable Configurable TDP
+/** Offset 0x1C10 - Enable Configurable TDP
Applies Configurable Processor Base Power (cTDP) initialization settings based on
non-cTDP or cTDP. Default is 1: Applies to cTDP; if 0 then applies non-cTDP and
BIOS will bypass cTDP initialzation flow
@@ -2937,42 +2942,42 @@ typedef struct {
**/
UINT8 ApplyConfigTdp;
-/** Offset 0x1C09 - Reserved
+/** Offset 0x1C11 - Reserved
**/
- UINT8 Reserved63;
+ UINT8 Reserved64;
-/** Offset 0x1C0A - Dual Tau Boost
+/** Offset 0x1C12 - Dual Tau Boost
Enable Dual Tau Boost feature. This is only applicable for Desktop 35W/65W/125W
sku. When DPTF is enabled this feature is ignored. <b>0: Disable</b>; 1: Enable
$EN_DIS
**/
UINT8 DualTauBoost;
-/** Offset 0x1C0B - Reserved
+/** Offset 0x1C13 - Reserved
**/
- UINT8 Reserved64[31];
+ UINT8 Reserved65[33];
-/** Offset 0x1C2A - End of Post message
+/** Offset 0x1C34 - End of Post message
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
**/
UINT8 EndOfPostMessage;
-/** Offset 0x1C2B - D0I3 Setting for HECI Disable
+/** Offset 0x1C35 - D0I3 Setting for HECI Disable
Test, 0: disable, 1: enable, Setting this option disables setting D0I3 bit for all
HECI devices
$EN_DIS
**/
UINT8 DisableD0I3SettingForHeci;
-/** Offset 0x1C2C - Mctp Broadcast Cycle
+/** Offset 0x1C36 - Mctp Broadcast Cycle
Test, Determine if MCTP Broadcast is enabled <b>0: Disable</b>; 1: Enable.
$EN_DIS
**/
UINT8 MctpBroadcastCycle;
-/** Offset 0x1C2D - ME Unconfig on RTC clear
+/** Offset 0x1C37 - ME Unconfig on RTC clear
0: Disable ME Unconfig On Rtc Clear. <b>1: Enable ME Unconfig On Rtc Clear</b>.
2: Cmos is clear, status unkonwn. 3: Reserved
0: Disable ME Unconfig On Rtc Clear, 1: Enable ME Unconfig On Rtc Clear, 2: Cmos
@@ -2980,159 +2985,159 @@ typedef struct {
**/
UINT8 MeUnconfigOnRtcClear;
-/** Offset 0x1C2E - Enforce Enhanced Debug Mode
+/** Offset 0x1C38 - Enforce Enhanced Debug Mode
Determine if ME should enter Enhanced Debug Mode. <b>0: disable</b>, 1: enable
$EN_DIS
**/
UINT8 EnforceEDebugMode;
-/** Offset 0x1C2F - Reserved
+/** Offset 0x1C39 - Reserved
**/
- UINT8 Reserved65[17];
+ UINT8 Reserved66[17];
-/** Offset 0x1C40 - Enable LOCKDOWN SMI
+/** Offset 0x1C4A - Enable LOCKDOWN SMI
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
$EN_DIS
**/
UINT8 PchLockDownGlobalSmi;
-/** Offset 0x1C41 - Enable LOCKDOWN BIOS Interface
+/** Offset 0x1C4B - Enable LOCKDOWN BIOS Interface
Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register.
$EN_DIS
**/
UINT8 PchLockDownBiosInterface;
-/** Offset 0x1C42 - Unlock all GPIO pads
+/** Offset 0x1C4C - Unlock all GPIO pads
Force all GPIO pads to be unlocked for debug purpose.
$EN_DIS
**/
UINT8 PchUnlockGpioPads;
-/** Offset 0x1C43 - PCH Unlock SideBand access
+/** Offset 0x1C4D - PCH Unlock SideBand access
The SideBand PortID mask for certain end point (e.g. PSFx) will be locked before
3rd party code execution. 0: Lock SideBand access; 1: Unlock SideBand access.
$EN_DIS
**/
UINT8 PchSbAccessUnlock;
-/** Offset 0x1C44 - Reserved
+/** Offset 0x1C4E - Reserved
**/
- UINT8 Reserved66[2];
+ UINT8 Reserved67[2];
-/** Offset 0x1C46 - PCIE RP Ltr Max Snoop Latency
+/** Offset 0x1C50 - PCIE RP Ltr Max Snoop Latency
Latency Tolerance Reporting, Max Snoop Latency.
**/
UINT16 PcieRpLtrMaxSnoopLatency[29];
-/** Offset 0x1C80 - PCIE RP Ltr Max No Snoop Latency
+/** Offset 0x1C8A - PCIE RP Ltr Max No Snoop Latency
Latency Tolerance Reporting, Max Non-Snoop Latency.
**/
UINT16 PcieRpLtrMaxNoSnoopLatency[29];
-/** Offset 0x1CBA - PCIE RP Snoop Latency Override Mode
+/** Offset 0x1CC4 - PCIE RP Snoop Latency Override Mode
Latency Tolerance Reporting, Snoop Latency Override Mode.
**/
UINT8 PcieRpSnoopLatencyOverrideMode[29];
-/** Offset 0x1CD7 - PCIE RP Snoop Latency Override Multiplier
+/** Offset 0x1CE1 - PCIE RP Snoop Latency Override Multiplier
Latency Tolerance Reporting, Snoop Latency Override Multiplier.
**/
UINT8 PcieRpSnoopLatencyOverrideMultiplier[29];
-/** Offset 0x1CF4 - PCIE RP Snoop Latency Override Value
+/** Offset 0x1CFE - PCIE RP Snoop Latency Override Value
Latency Tolerance Reporting, Snoop Latency Override Value.
**/
UINT16 PcieRpSnoopLatencyOverrideValue[29];
-/** Offset 0x1D2E - PCIE RP Non Snoop Latency Override Mode
+/** Offset 0x1D38 - PCIE RP Non Snoop Latency Override Mode
Latency Tolerance Reporting, Non-Snoop Latency Override Mode.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMode[29];
-/** Offset 0x1D4B - PCIE RP Non Snoop Latency Override Multiplier
+/** Offset 0x1D55 - PCIE RP Non Snoop Latency Override Multiplier
Latency Tolerance Reporting, Non-Snoop Latency Override Multiplier.
**/
UINT8 PcieRpNonSnoopLatencyOverrideMultiplier[29];
-/** Offset 0x1D68 - PCIE RP Non Snoop Latency Override Value
+/** Offset 0x1D72 - PCIE RP Non Snoop Latency Override Value
Latency Tolerance Reporting, Non-Snoop Latency Override Value.
**/
UINT16 PcieRpNonSnoopLatencyOverrideValue[29];
-/** Offset 0x1DA2 - PCIE RP Slot Power Limit Scale
+/** Offset 0x1DAC - PCIE RP Slot Power Limit Scale
Specifies scale used for slot power limit value. Leave as 0 to set to default.
**/
UINT8 PcieRpSlotPowerLimitScale[29];
-/** Offset 0x1DBF - Reserved
+/** Offset 0x1DC9 - Reserved
**/
- UINT8 Reserved67;
+ UINT8 Reserved68;
-/** Offset 0x1DC0 - PCIE RP Slot Power Limit Value
+/** Offset 0x1DCA - PCIE RP Slot Power Limit Value
Specifies upper limit on power supplie by slot. Leave as 0 to set to default.
**/
UINT16 PcieRpSlotPowerLimitValue[29];
-/** Offset 0x1DFA - PCIE RP Enable Port8xh Decode
+/** Offset 0x1E04 - PCIE RP Enable Port8xh Decode
This member describes whether PCIE root port Port 8xh Decode is enabled. 0: Disable;
1: Enable.
$EN_DIS
**/
UINT8 PcieEnablePort8xhDecode;
-/** Offset 0x1DFB - PCIE Port8xh Decode Port Index
+/** Offset 0x1E05 - PCIE Port8xh Decode Port Index
The Index of PCIe Port that is selected for Port8xh Decode (0 Based).
**/
UINT8 PchPciePort8xhDecodePortIndex;
-/** Offset 0x1DFC - PCH Energy Reporting
+/** Offset 0x1E06 - PCH Energy Reporting
Disable/Enable PCH to CPU energy report feature.
$EN_DIS
**/
UINT8 PchPmDisableEnergyReport;
-/** Offset 0x1DFD - PCH Sata Test Mode
+/** Offset 0x1E07 - PCH Sata Test Mode
Allow entrance to the PCH SATA test modes.
$EN_DIS
**/
UINT8 SataTestMode;
-/** Offset 0x1DFE - PCH USB OverCurrent mapping lock enable
+/** Offset 0x1E08 - PCH USB OverCurrent mapping lock enable
If this policy option is enabled then BIOS will program OCCFDONE bit in xHCI meaning
that OC mapping data will be consumed by xHCI and OC mapping registers will be locked.
$EN_DIS
**/
UINT8 PchXhciOcLock;
-/** Offset 0x1DFF - Low Power Mode Enable/Disable config mask
+/** Offset 0x1E09 - Low Power Mode Enable/Disable config mask
Configure if respective S0i2/3 sub-states are to be supported. Each bit corresponds
to one sub-state (LPMx - BITx): LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4.
**/
UINT8 PmcLpmS0ixSubStateEnableMask;
-/** Offset 0x1E00 - Reserved
+/** Offset 0x1E0A - Reserved
**/
- UINT8 Reserved68[5];
+ UINT8 Reserved69[5];
-/** Offset 0x1E05 - PMC C10 dynamic threshold dajustment enable
+/** Offset 0x1E0F - PMC C10 dynamic threshold dajustment enable
Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
$EN_DIS
**/
UINT8 PmcC10DynamicThresholdAdjustment;
-/** Offset 0x1E06 - Reserved
+/** Offset 0x1E10 - Reserved
**/
- UINT8 Reserved69[34];
+ UINT8 Reserved70[36];
-/** Offset 0x1E28 - FspEventHandler
+/** Offset 0x1E34 - FspEventHandler
<b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
**/
UINT32 FspEventHandler;
-/** Offset 0x1E2C - Reserved
+/** Offset 0x1E38 - Reserved
**/
- UINT8 Reserved70[20];
+ UINT8 Reserved71[24];
} FSP_S_CONFIG;
/** Fsp S UPD Configuration
@@ -3151,11 +3156,11 @@ typedef struct {
**/
FSP_S_CONFIG FspsConfig;
-/** Offset 0x1E40
+/** Offset 0x1E50
**/
UINT8 Rsvd600[6];
-/** Offset 0x1E46
+/** Offset 0x1E56
**/
UINT16 UpdTerminator;
} FSPS_UPD;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 01:51:48 +0000