diff options
| author | Tim Chu <Tim.Chu@quantatw.com> | 2020-11-12 02:56:59 -0800 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-11-20 00:51:03 +0000 |
| commit | 957a36397ad7edc004f1f432a26ed43f86480bbf (patch) | |
| tree | 294d80c2823fbc454f4b8923b70a63efa44ad128 /src/vendorcode/intel/fsp/fsp2_0 | |
| parent | 051ee4e3ad14861b64ddb1da5af473812770279a (diff) | |
vc/intel/fsp/fsp2_0/cpx_sp: Expose RasModesEnabled field in
SystemMemoryMapHob
This field from SystemMemoryMapHob can be used to define error
correction type in SMBIOS type 16.
Tested=On OCP Delta Lake, the value is expected.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I0009a287a64f16e926f682e389af3248aeb85bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47505
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h | 22 |
1 files changed, 17 insertions, 5 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h index 1a4023f437..53b73053c0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -36,6 +36,16 @@ are permitted provided that the following conditions are met: 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \ } +/* Bit definitions for RasModes */ +#define CH_INDEPENDENT 0 +#define FULL_MIRROR_1LM BIT0 +#define FULL_MIRROR_2LM BIT1 +#define CH_LOCKSTEP BIT2 +#define RK_SPARE BIT3 +#define PARTIAL_MIRROR_1LM BIT5 +#define PARTIAL_MIRROR_2LM BIT6 +#define STAT_VIRT_LOCKSTEP BIT7 + #define MEMTYPE_1LM_MASK (1 << 0) #define MEMTYPE_2LM_MASK (1 << 1) #define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) @@ -143,21 +153,23 @@ typedef struct SystemMemoryMapHob { UINT8 reserved2[22]; UINT8 DdrVoltage; - UINT8 reserved3[38]; + UINT8 reserved3[33]; + UINT8 RasModesEnabled; // RAS modes that are enabled + UINT8 reserved4[4]; UINT8 NumChPerMC; UINT8 numberEntries; // Number of Memory Map Elements SYSTEM_MEMORY_MAP_ELEMENT Element[(MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES) + MAX_FPGA_REMOTE_SAD_RULES]; - UINT8 reserved4[2216]; + UINT8 reserved5[2216]; MEMMAP_SOCKET Socket[MAX_SOCKET]; - UINT8 reserved5[1603]; + UINT8 reserved6[1603]; UINT16 BiosFisVersion; // Firmware Interface Specification version currently supported by BIOS - UINT8 reserved6[24]; + UINT8 reserved7[24]; UINT32 MmiohBase; // MMIOH base in 64MB granularity - UINT8 reserved7[5]; + UINT8 reserved8[5]; } SYSTEM_MEMORY_MAP_HOB; |