diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-08-30 13:51:44 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-09-01 03:06:04 +0000 |
| commit | 8e6d5f2937c169914e46b5ebc973e5df5e4290a7 (patch) | |
| tree | 1550c8877877a7a9b197da65bcff76f878bee560 /src/vendorcode/intel/fsp/fsp2_0 | |
| parent | b7a68d5b05259a07a84a546e6a7e40948ba705ac (diff) | |
{include,mb,soc,sb,vendorcode}: Make hexadecimal notation consistent
Convert 0X -> 0x
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: Iea3ca67908135d0e85083a05bad2ea176ca34095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index 770390d606..05210d6801 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -683,7 +683,7 @@ typedef struct { /** Offset 0x0124 - PCIe Disable Spread Spectrum Clocking PCIe Disable Spread Spectrum Clocking. Normal Operation(0x0)(Default) - SSC enabled, - Disable SSC(0X1) - Disable SSC per platform design or for compliance testing + Disable SSC(0x1) - Disable SSC per platform design or for compliance testing 0:Normal Operation, 1:Disable SSC **/ UINT8 PegDisableSpreadSpectrumClocking; |