diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2017-11-08 22:27:54 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-12-08 23:27:01 +0000 |
| commit | 5773c4ce026b23caf941af7933b43548ab2dea8f (patch) | |
| tree | 672d63a6f39374e66e00bdbb6ac092ef0ed45bc3 /src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h | |
| parent | ea17304e6426ba83cee0516dc3b838c26dd0e5a8 (diff) | |
vendorcode/intel/fsp/fsp2_0/glk: Update header files as per v69_51
Update FSP header files to match FSP v69_51.
UPD updates in FSP v69_51 are:
- SGX Epoch
- Sub/System Vendor ID
- Remove deprecated UPD
Change-Id: I7298615a6e051061b948814a1cd9cbd42f6574b5
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/22391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h | 28 |
1 files changed, 16 insertions, 12 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h index 6db66854be..acbc59695a 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspmUpd.h @@ -913,13 +913,7 @@ typedef struct { **/ UINT8 EnableSgx; -/** Offset 0x014B - PRMRR size - PRMRR size. 0:Invalid (default), 1:32MB, 2:64MB 3:128MB - 0:Invalid (default), 1:32MB, 2:64MB 3:128MB -**/ - UINT32 PrmrrSize; - -/** Offset 0x014F - Periodic Retraining Disable +/** Offset 0x014B - Periodic Retraining Disable Periodic Retraining Disable - This option allows customers to disable LPDDR4 Periodic Retraining for debug purposes. Periodic Retraining should be enabled in production. Periodic retraining allows the platform to operate reliably over a larger voltage @@ -930,6 +924,12 @@ typedef struct { **/ UINT8 PeriodicRetrainingDisable; +/** Offset 0x014C - PRMRR size + PRMRR size. 0:Invalid (default), 1:32MB, 2:64MB 3:128MB + 0:Invalid (default), 1:32MB, 2:64MB 3:128MB +**/ + UINT32 PrmrrSize; + /** Offset 0x0150 - Enable Reset System Enable FSP to trigger reset instead of returning reset request. 0x00: Return the Return Status from FSP if a reset is required. (default); 0x01: Perform Reset inside @@ -977,18 +977,18 @@ typedef struct { /** Offset 0x016C **/ - UINT8 ReservedFspmTestUpd[18]; + UINT8 ReservedFspmTestUpd[20]; } FSP_M_TEST_CONFIG; /** Fsp M Restricted Configuration **/ typedef struct { -/** Offset 0x017E +/** Offset 0x0180 **/ UINT32 Signature; -/** Offset 0x0182 +/** Offset 0x0184 **/ UINT8 ReservedFspmRestrictedUpd[124]; } FSP_M_RESTRICTED_CONFIG; @@ -1013,11 +1013,15 @@ typedef struct { **/ FSP_M_TEST_CONFIG FspmTestConfig; -/** Offset 0x017E +/** Offset 0x0180 **/ FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; -/** Offset 0x01FE +/** Offset 0x0200 +**/ + UINT8 UnusedUpdSpace1[6]; + +/** Offset 0x0206 **/ UINT16 UpdTerminator; } FSPM_UPD; |