diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-11-09 17:39:39 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-11 21:08:56 +0000 |
| commit | 8e3b5e849cc4437486a33acb1ad4e4b7ce195989 (patch) | |
| tree | d82536085071ec5e89cfc77e9c81ffb2b0d9facd /src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h | |
| parent | 16995fb7eacf3a2b946795ab327c3c1764ab81ca (diff) | |
intel/fsp: Update cannonlake FSP header
Update cannonlake FSP header to revision 7.x.11.43. Following changes
had been made:
1.Remove Minimum control ration from FSPM UPD.
2.Add Intersil VR command option in FSPS UPD.
3.Add minimum and maxiam ring ratio override.
TEST=None
Change-Id: I63c990e5766370a82dc1c044bcf744612229a605
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h index dded50d383..876c9d264c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h @@ -917,10 +917,9 @@ typedef struct { **/ UINT8 CoreVoltageMode; -/** Offset 0x0207 - Minimum clr turbo ratio override - Minimum clr turbo ratio override. <b>0: Hardware defaults.</b> Range: 0-83 +/** Offset 0x0207 **/ - UINT8 RingMinOcRatio; + UINT8 UnusedUpdSpace6; /** Offset 0x0208 - Maximum clr turbo ratio override Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the @@ -1075,7 +1074,7 @@ typedef struct { /** Offset 0x0227 **/ - UINT8 UnusedUpdSpace6; + UINT8 UnusedUpdSpace7; /** Offset 0x0228 - PrmrrSize 0=Invalid, 32MB=0x2000000, 64MB=0x4000000, 128MB=0x8000000, 256MB=0x10000000 @@ -1853,7 +1852,7 @@ typedef struct { /** Offset 0x04C7 **/ - UINT8 UnusedUpdSpace7; + UINT8 UnusedUpdSpace8; /** Offset 0x04C8 - RAPL PL 2 Power range[0;2^14-1]= [2047.875;0]in W, (224= Def) @@ -2481,7 +2480,7 @@ typedef struct { /** Offset 0x0579 **/ - UINT8 UnusedUpdSpace8; + UINT8 UnusedUpdSpace9; /** Offset 0x057A - Jitter Dwell Time for PCIe Gen3 Software Equalization Range: 0-65535, default is 1000. @warning Do not change from the default |