diff options
| author | Brandon Breitenstein <brandon.breitenstein@intel.com> | 2016-10-03 15:38:54 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-10-07 19:13:53 +0200 |
| commit | 7692807f4f27a045c0e3638319528c7ae0873d57 (patch) | |
| tree | eec86d5bd8bea597d0f33c3a612b991010a8ca4a /src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h | |
| parent | 2e6aeba9ca442f5db23a3eef73f7eead82f596e9 (diff) | |
vendorcode/intel/fsp: Update UPD headers for FSP 157_10
These header files contain a few new UPDs. The EnableS3Heci2
UPD will be used to save ~100ms from the S3 resume time on
Apollolake chrome platforms.
BUG=chrome-os-partner:58121
BRANCH=none
TEST=built coreboot for reef and verified no regressions
Change-Id: I1f324d00237c7150697800258a2f7b7eed856417
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16869
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h')
| -rw-r--r-- | src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h | 36 |
1 files changed, 27 insertions, 9 deletions
diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h index 553eba3f18..311980774b 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h @@ -530,6 +530,7 @@ typedef struct { /** Offset 0x009F - HD-Audio BIOS Configuration Lock Down Enable/Disable HD-Audio BIOS Configuration Lock Down. 0:Disable(Default), 1:Enable. + This option is deprecated $EN_DIS **/ UINT8 BiosCfgLockDown; @@ -1480,20 +1481,37 @@ typedef struct { **/ UINT8 MonitorMwaitEnable; -/** Offset 0x0328 +/** Offset 0x0328 - IRQ Interrupt Polarity Control + Set IRQ Interrupt Polarity Control to ITSS.IPC[0]~IPC[3]. 0:Active High, 1:Active Low **/ - UINT8 ReservedFspsUpd[8]; + UINT32 IPC[4]; + +/** Offset 0x0338 - Disable ModPHY dynamic power gate + Disable ModPHY dynamic power gate for the specific SATA port. +**/ + UINT8 SataPortsDisableDynamicPg[2]; + +/** Offset 0x033A - Universal Audio Architecture compliance for DSP enabled system + 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox + driver or SST driver supported). + $EN_DIS +**/ + UINT8 HdAudioDspUaaCompliance; + +/** Offset 0x033B +**/ + UINT8 ReservedFspsUpd[5]; } FSP_S_CONFIG; /** Fsp S Test Configuration **/ typedef struct { -/** Offset 0x0330 +/** Offset 0x0340 **/ UINT32 Signature; -/** Offset 0x0334 +/** Offset 0x0344 **/ UINT8 ReservedFspsTestUpd[12]; } FSP_S_TEST_CONFIG; @@ -1502,11 +1520,11 @@ typedef struct { **/ typedef struct { -/** Offset 0x0340 +/** Offset 0x0350 **/ UINT32 Signature; -/** Offset 0x0344 +/** Offset 0x0354 **/ UINT8 ReservedFspsRestrictedUpd[12]; } FSP_S_RESTRICTED_CONFIG; @@ -1523,15 +1541,15 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0330 +/** Offset 0x0340 **/ FSP_S_TEST_CONFIG FspsTestConfig; -/** Offset 0x0340 +/** Offset 0x0350 **/ FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; -/** Offset 0x0350 +/** Offset 0x0360 **/ UINT16 UpdTerminator; } FSPS_UPD; |