diff options
| author | David Wu <david_wu@quanta.corp-partner.google.com> | 2020-09-08 15:30:29 +0800 |
|---|---|---|
| committer | Edward O'Callaghan <quasisec@chromium.org> | 2020-09-09 00:11:58 +0000 |
| commit | 299cb4bb8af9be08d1a5a39e23c6ff7cd96c1ad5 (patch) | |
| tree | e9323023f6790f1d900d3b86a0882a9675fe5a18 /src/vendorcode/intel/fsp/fsp2_0/alderlake | |
| parent | 8e0f9f30f666de37238fa42b1bd33f33ae99c0fb (diff) | |
mb/google/puff: Increase DPTF parameters for faffy
Update critical and passive policy for TSR0.
BUG=b:167477885
BRANCH=puff
TEST=build and verify by thermal team
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I244e1b5cacabf5b73c47b4039ae150cd17fcd0fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45169
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/alderlake')
0 files changed, 0 insertions, 0 deletions