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| author | Yidi Lin <yidi.lin@mediatek.com> | 2020-11-20 14:03:20 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2020-11-21 13:36:23 +0000 |
| commit | aad4651e3eab260c94058536d373b2ff22b40d92 (patch) | |
| tree | c2ed69daf358d06b97360eabd74371b577969a9a /src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h | |
| parent | 1e37c9ca465a14d55adeacb332354771543437b5 (diff) | |
mb/google/asurada: Get RAM code from ADC 3
On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Asurada the RAM code can be
read from ADC channel 3.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h')
0 files changed, 0 insertions, 0 deletions