vendorcode/{amd,cavium,intel}: Remove trailing whitespace

find src -type f "!" -regex ".*\.\(vbt\|bin\)" -exec sed -i -e "s,\s\+$,,g" {} \;

Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30959
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 4 insertions, 4 deletions

diff --git a/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h b/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h
index 6a621d688c..44777f5745 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h
@@ -218,7 +218,7 @@ EFI_STATUS
   and defined for each FSP binary. This will be documented in Integration guide with
   each FSP release.
   After FspMemInit completes its execution, it passes the pointer to the HobList and
-  returns to the boot loader from where it was called. Bootloader is responsible to 
+  returns to the boot loader from where it was called. Bootloader is responsible to
   migrate it's stack and data to Memory.
   FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
   complete the silicon initialization and provides bootloader an opportunity to get
diff --git a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h
index 32b926a6d4..fddc168701 100644
--- a/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h
+++ b/src/vendorcode/intel/fsp/fsp1_1/skylake/FspUpdVpd.h
@@ -693,7 +693,7 @@ typedef struct {
   UINT8                       LanLtrEnable;
 
 /** Offset 0x033D - SATA eSATASpeedLimit
-  When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable. 
+  When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSATA port speed. 0: disable, 1: enable.
   $EN_DIS
 **/
   UINT8                       eSATASpeedLimit;
@@ -1030,7 +1030,7 @@ typedef struct {
 } UPD_DATA_REGION;
 
 #define FSP_IMAGE_ID    0x245053464C4B5324        /* '$SKLFSP$' */
-#define FSP_IMAGE_REV   0x01090000 
+#define FSP_IMAGE_REV   0x01090000
 
 /** VPD data structure
 **/
@@ -1054,7 +1054,7 @@ typedef struct {
   UINT8                       UnusedVpdSpace0[32];
 
 /** Offset 0x0030 - PcdSerialIoUartDebugEnable
-  Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP. 
+  Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
   0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
 **/
   UINT8                       PcdSerialIoUartDebugEnable;