vendorcode/intel: Add edk2-stable202005 support

This patch includes (edk2/edk2-stable202005) all required headers
for edk2-stable202005 quarterly EDK2 tag from EDK2 github project
using below command:
>> git clone https://github.com/tianocore/edk2.git vedk2-stable202005

Only include necessary header files.

MdePkg/Include/Base.h was updated to avoid compilation errors through
safeguarding definitions for MIN, MAX, NULL, ABS, ARRAY_SIZE.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3172505d9b829647ee1208c87623172f10b39310
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42239
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 68 insertions, 0 deletions

diff --git a/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SdramSpd.h b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SdramSpd.h
new file mode 100644
index 0000000000..30958588a0
--- /dev/null
+++ b/src/vendorcode/intel/edk2/edk2-stable202005/MdePkg/Include/IndustryStandard/SdramSpd.h
@@ -0,0 +1,68 @@
+/** @file
+  This file contains definitions for the SPD fields on an SDRAM.
+
+  Copyright (c) 2007 - 2016, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SDRAM_SPD_H_
+#define _SDRAM_SPD_H_
+
+#include <IndustryStandard/SdramSpdDdr3.h>
+#include <IndustryStandard/SdramSpdDdr4.h>
+#include <IndustryStandard/SdramSpdLpDdr.h>
+
+//
+// SDRAM SPD field definitions
+//
+#define SPD_MEMORY_TYPE                 2
+#define SPD_SDRAM_ROW_ADDR              3
+#define SPD_SDRAM_COL_ADDR              4
+#define SPD_SDRAM_MODULE_ROWS           5
+#define SPD_SDRAM_MODULE_DATA_WIDTH_LSB 6
+#define SPD_SDRAM_MODULE_DATA_WIDTH_MSB 7
+#define SPD_SDRAM_ECC_SUPPORT           11
+#define SPD_SDRAM_REFRESH               12
+#define SPD_SDRAM_WIDTH                 13
+#define SPD_SDRAM_ERROR_WIDTH           14
+#define SPD_SDRAM_BURST_LENGTH          16
+#define SPD_SDRAM_NO_OF_BANKS           17
+#define SPD_SDRAM_CAS_LATENCY           18
+#define SPD_SDRAM_MODULE_ATTR           21
+
+#define SPD_SDRAM_TCLK1_PULSE           9   ///< cycle time for highest cas latency
+#define SPD_SDRAM_TAC1_PULSE            10  ///< access time for highest cas latency
+#define SPD_SDRAM_TCLK2_PULSE           23  ///< cycle time for 2nd highest cas latency
+#define SPD_SDRAM_TAC2_PULSE            24  ///< access time for 2nd highest cas latency
+#define SPD_SDRAM_TCLK3_PULSE           25  ///< cycle time for 3rd highest cas latency
+#define SPD_SDRAM_TAC3_PULSE            26  ///< access time for 3rd highest cas latency
+#define SPD_SDRAM_MIN_PRECHARGE         27
+#define SPD_SDRAM_ACTIVE_MIN            28
+#define SPD_SDRAM_RAS_CAS               29
+#define SPD_SDRAM_RAS_PULSE             30
+#define SPD_SDRAM_DENSITY               31
+
+//
+// Memory Type Definitions
+//
+#define SPD_VAL_SDR_TYPE  4       ///< SDR SDRAM memory
+#define SPD_VAL_DDR_TYPE  7       ///< DDR SDRAM memory
+#define SPD_VAL_DDR2_TYPE 8       ///< DDR2 SDRAM memory
+#define SPD_VAL_DDR3_TYPE 11      ///< DDR3 SDRAM memory
+#define SPD_VAL_DDR4_TYPE 12      ///< DDR4 SDRAM memory
+#define SPD_VAL_LPDDR3_TYPE 15    ///< LPDDR3 SDRAM memory
+#define SPD_VAL_LPDDR4_TYPE 16    ///< LPDDR4 SDRAM memory
+
+//
+// ECC Type Definitions
+//
+#define SPD_ECC_TYPE_NONE   0x00  ///< No error checking
+#define SPD_ECC_TYPE_PARITY 0x01  ///< No error checking
+#define SPD_ECC_TYPE_ECC    0x02  ///< Error checking only
+//
+// Module Attributes (Bit positions)
+//
+#define SPD_BUFFERED    0x01
+#define SPD_REGISTERED  0x02
+
+#endif