vendorcode/{amd,cavium,intel}: Remove trailing whitespace

find src -type f "!" -regex ".*\.\(vbt\|bin\)" -exec sed -i -e "s,\s\+$,,g" {} \;

Change-Id: Ic70cf8524dcd0a0f5700f91b704b3c545dd8a01a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30959
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 14 insertions, 14 deletions

diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PciSegmentLib.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PciSegmentLib.h
index b1e5301925..a1fc7a1fa6 100644
--- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PciSegmentLib.h
+++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Library/PciSegmentLib.h
@@ -1,11 +1,11 @@
 /** @file
   Provides services to access PCI Configuration Space on a platform with multiple PCI segments.
-  
+
   The PCI Segment Library function provide services to read, write, and modify the PCI configuration
-  registers on PCI root bridges on any supported PCI segment.  These library services take a single 
-  address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.  
+  registers on PCI root bridges on any supported PCI segment.  These library services take a single
+  address parameter that encodes the PCI Segment, PCI Bus, PCI Device, PCI Function, and PCI Register.
   The layout of this address parameter is as follows:
-  
+
             PCI Register: Bits 0..11
             PCI Function  Bits 12..14
             PCI Device  Bits 15..19
@@ -13,15 +13,15 @@
             Reserved  Bits 28..31.  Must be 0.
             PCI Segment Bits 32..47
             Reserved  Bits 48..63.  Must be 0.
-            
+
   | Reserved (MBZ) | Segment | Reserved (MBZ) |     Bus     | Device | Function | Register |
   63             48  47    32  31           28 27         20 19    15 14      12 11         0
 
-  These functions perform PCI configuration cycles using the default PCI configuration access 
-  method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it 
-  may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate 
-  access method.  Modules will typically use the PCI Segment Library for its PCI configuration 
-  accesses when PCI Segments other than Segment #0 must be accessed.  
+  These functions perform PCI configuration cycles using the default PCI configuration access
+  method.  This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, or it
+  may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some alternate
+  access method.  Modules will typically use the PCI Segment Library for its PCI configuration
+  accesses when PCI Segments other than Segment #0 must be accessed.
 
 Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>
 This program and the accompanying materials
@@ -71,16 +71,16 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
   )
 
 /**
-  Register a PCI device so PCI configuration registers may be accessed after 
+  Register a PCI device so PCI configuration registers may be accessed after
   SetVirtualAddressMap().
-  
+
   If any reserved bits in Address are set, then ASSERT().
 
   @param  Address Address that encodes the PCI Bus, Device, Function and
                   Register.
-  
+
   @retval RETURN_SUCCESS           The PCI device was registered for runtime access.
-  @retval RETURN_UNSUPPORTED       An attempt was made to call this function 
+  @retval RETURN_UNSUPPORTED       An attempt was made to call this function
                                    after ExitBootServices().
   @retval RETURN_UNSUPPORTED       The resources required to access the PCI device
                                    at runtime could not be mapped.