vendorcode/intel: Add UDK 2015 Bindings

Add UDK 2015 Bindings for FSP header compatibility.
These bindings add the necessary code to read FSP Headers
without any modifications from FSP Source.

BUG=chrome-os-partner:54100
BRANCH=none
TEST=built coreboot image and verified boot

Change-Id: I2887f55b6e63cd0a2b2add9a521be9cfaf875e7d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16307
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

8 files changed, 747 insertions, 0 deletions

diff --git a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspDataTable.h b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspDataTable.h
new file mode 100644
index 0000000000..09fc8471db
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspDataTable.h
@@ -0,0 +1,32 @@
+/** @file
+  The header file of FSP data table
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  This file and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSP_DATA_TABLE_H_
+#define _FSP_DATA_TABLE_H_
+
+#pragma pack(1)
+
+#define FSP_DATA_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'D')
+
+typedef struct  {
+  UINT32  Signature;
+  UINT32  Length;
+  UINT32  FsptBase;
+  UINT32  FspmBase;
+  UINT32  FspsBase;
+} FSP_DATA_TABLE;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas.h b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas.h
new file mode 100644
index 0000000000..21b84a3069
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas.h
@@ -0,0 +1,24 @@
+/** @file
+  Intel FSP definition from Intel Firmware Support Package External
+  Architecture Specification v2.0.
+
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  This file and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSP_EAS_H_
+#define _FSP_EAS_H_
+
+#include <Uefi.h>
+#include <Guid/GuidHobFspEas.h>
+#include <Guid/FspHeaderFile.h>
+#include <FspEas/FspApi.h>
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas/FspApi.h
new file mode 100644
index 0000000000..c58b169f99
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspEas/FspApi.h
@@ -0,0 +1,288 @@
+/** @file
+  Intel FSP API definition from Intel Firmware Support Package External
+  Architecture Specification v2.0.
+
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  This file and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSP_API_H_
+#define _FSP_API_H_
+
+///
+/// FSP Reset Status code
+/// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code
+/// @{
+#define FSP_STATUS_RESET_REQUIRED_COLD         0x40000001
+#define FSP_STATUS_RESET_REQUIRED_WARM         0x40000002
+#define FSP_STATUS_RESET_REQUIRED_3            0x40000003
+#define FSP_STATUS_RESET_REQUIRED_4            0x40000004
+#define FSP_STATUS_RESET_REQUIRED_5            0x40000005
+#define FSP_STATUS_RESET_REQUIRED_6            0x40000006
+#define FSP_STATUS_RESET_REQUIRED_7            0x40000007
+#define FSP_STATUS_RESET_REQUIRED_8            0x40000008
+/// @}
+
+#pragma pack(1)
+///
+/// FSP_UPD_HEADER Configuration.
+///
+typedef struct {
+  ///
+  /// UPD Region Signature. This signature will be
+  /// "XXXXXX_T" for FSP-T
+  /// "XXXXXX_M" for FSP-M
+  /// "XXXXXX_S" for FSP-S
+  /// Where XXXXXX is an unique signature
+  ///
+  UINT64                      Signature;
+  ///
+  /// Revision of the Data structure. For FSP v2.0 value is 1.
+  ///
+  UINT8                       Revision;
+  UINT8                       Reserved[23];
+} FSP_UPD_HEADER;
+
+///
+/// FSPM_ARCH_UPD Configuration.
+///
+typedef struct {
+  ///
+  /// Revision of the structure. For FSP v2.0 value is 1.
+  ///
+  UINT8                       Revision;
+  UINT8                       Reserved[3];
+  ///
+  /// Pointer to the non-volatile storage (NVS) data buffer.
+  /// If it is NULL it indicates the NVS data is not available.
+  ///
+  VOID                        *NvsBufferPtr;
+  ///
+  /// Pointer to the temporary stack base address to be
+  /// consumed inside FspMemoryInit() API.
+  ///
+  VOID                        *StackBase;
+  ///
+  /// Temporary stack size to be consumed inside
+  /// FspMemoryInit() API.
+  ///
+  UINT32                      StackSize;
+  ///
+  /// Size of memory to be reserved by FSP below "top
+  /// of low usable memory" for bootloader usage.
+  ///
+  UINT32                      BootLoaderTolumSize;
+  ///
+  /// Current boot mode.
+  ///
+  UINT32                      BootMode;
+  UINT8                       Reserved1[8];
+} FSPM_ARCH_UPD;
+
+///
+/// FSPT_UPD_COMMON Configuration.
+///
+typedef struct {
+  ///
+  /// FSP_UPD_HEADER Configuration.
+  ///
+  FSP_UPD_HEADER              FspUpdHeader;
+} FSPT_UPD_COMMON;
+
+///
+/// FSPM_UPD_COMMON Configuration.
+///
+typedef struct {
+  ///
+  /// FSP_UPD_HEADER Configuration.
+  ///
+  FSP_UPD_HEADER              FspUpdHeader;
+  ///
+  /// FSPM_ARCH_UPD Configuration.
+  ///
+  FSPM_ARCH_UPD               FspmArchUpd;
+} FSPM_UPD_COMMON;
+
+///
+/// FSPS_UPD_COMMON Configuration.
+///
+typedef struct {
+  ///
+  /// FSP_UPD_HEADER Configuration.
+  ///
+  FSP_UPD_HEADER              FspUpdHeader;
+} FSPS_UPD_COMMON;
+
+///
+/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE.
+///
+typedef enum {
+  ///
+  /// This stage is notified when the bootloader completes the
+  /// PCI enumeration and the resource allocation for the
+  /// PCI devices is complete.
+  ///
+  EnumInitPhaseAfterPciEnumeration = 0x20,
+  ///
+  /// This stage is notified just before the bootloader hand-off
+  /// to the OS loader.
+  ///
+  EnumInitPhaseReadyToBoot         = 0x40,
+  ///
+  /// This stage is notified just before the firmware/Preboot
+  /// environment transfers management of all system resources
+  /// to the OS or next level execution environment.
+  ///
+  EnumInitPhaseEndOfFirmware       = 0xF0
+} FSP_INIT_PHASE;
+
+///
+/// Definition of NOTIFY_PHASE_PARAMS.
+///
+typedef struct {
+  ///
+  /// Notification phase used for NotifyPhase API
+  ///
+  FSP_INIT_PHASE     Phase;
+} NOTIFY_PHASE_PARAMS;
+
+#pragma pack()
+
+/**
+  This FSP API is called soon after coming out of reset and before memory and stack is
+  available. This FSP API will load the microcode update, enable code caching for the
+  region specified by the boot loader and also setup a temporary stack to be used until
+  main memory is initialized.
+
+  A hardcoded stack can be set up with the following values, and the "esp" register
+  initialized to point to this hardcoded stack.
+  1. The return address where the FSP will return control after setting up a temporary
+     stack.
+  2. A pointer to the input parameter structure
+
+  However, since the stack is in ROM and not writeable, this FSP API cannot be called
+  using the "call" instruction, but needs to be jumped to.
+
+  @param[in] FsptUpdDataPtr     Pointer to the FSPT_UPD data structure.
+
+  @retval EFI_SUCCESS           Temporary RAM was initialized successfully.
+  @retval EFI_INVALID_PARAMETER Input parameters are invalid.
+  @retval EFI_UNSUPPORTED       The FSP calling conditions were not met.
+  @retval EFI_DEVICE_ERROR      Temp RAM initialization failed.
+
+  If this function is successful, the FSP initializes the ECX and EDX registers to point to
+  a temporary but writeable memory range available to the boot loader and returns with
+  FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary
+  memory range and EDX points to the end of the range. Boot loader is free to use the
+  whole range described. Typically the boot loader can reload the ESP register to point
+  to the end of this returned range so that it can be used as a standard stack.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_TEMP_RAM_INIT) (
+  IN  VOID    *FsptUpdDataPtr
+  );
+
+/**
+  This FSP API is used to notify the FSP about the different phases in the boot process.
+  This allows the FSP to take appropriate actions as needed during different initialization
+  phases. The phases will be platform dependent and will be documented with the FSP
+  release. The current FSP supports two notify phases:
+    Post PCI enumeration
+    Ready To Boot
+
+  @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS
+
+  @retval EFI_SUCCESS           The notification was handled successfully.
+  @retval EFI_UNSUPPORTED       The notification was not called in the proper order.
+  @retval EFI_INVALID_PARAMETER The notification code is invalid.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_NOTIFY_PHASE) (
+  IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr
+  );
+
+/**
+  This FSP API is called after TempRamInit and initializes the memory.
+  This FSP API accepts a pointer to a data structure that will be platform dependent
+  and defined for each FSP binary. This will be documented in Integration guide with
+  each FSP release.
+  After FspMemInit completes its execution, it passes the pointer to the HobList and
+  returns to the boot loader from where it was called. BootLoader is responsible to
+  migrate it's stack and data to Memory.
+  FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
+  complete the silicon initialization and provides bootloader an opportunity to get
+  control after system memory is available and before the temporary RAM is torn down.
+
+  @param[in]  FspmUpdDataPtr          Pointer to the FSPM_UPD data sructure.
+  @param[out] HobListPtr              Pointer to receive the address of the HOB list.
+
+  @retval EFI_SUCCESS                 FSP execution environment was initialized successfully.
+  @retval EFI_INVALID_PARAMETER       Input parameters are invalid.
+  @retval EFI_UNSUPPORTED             The FSP calling conditions were not met.
+  @retval EFI_DEVICE_ERROR            FSP initialization failed.
+  @retval EFI_OUT_OF_RESOURCES        Stack range requested by FSP is not met.
+  @retval FSP_STATUS_RESET_REQUIREDx  A reset is reuired. These status codes will not be returned during S3.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_MEMORY_INIT) (
+  IN  VOID    *FspmUpdDataPtr,
+  OUT VOID    **HobListPtr
+  );
+
+
+/**
+  This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary
+  memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure
+  that will be platform dependent and defined for each FSP binary. This will be
+  documented in Integration Guide.
+  FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to
+  complete the silicon initialization and provides bootloader an opportunity to get
+  control after system memory is available and before the temporary RAM is torn down.
+
+  @param[in] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure.
+                                 This structure is normally defined in the Integration Guide.
+                                 And if it is not defined in the Integration Guide, pass NULL.
+
+  @retval EFI_SUCCESS            FSP execution environment was initialized successfully.
+  @retval EFI_INVALID_PARAMETER  Input parameters are invalid.
+  @retval EFI_UNSUPPORTED        The FSP calling conditions were not met.
+  @retval EFI_DEVICE_ERROR       FSP initialization failed.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_TEMP_RAM_EXIT) (
+  IN  VOID    *TempRamExitParamPtr
+  );
+
+
+/**
+  This FSP API is called after TempRamExit API.
+  FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the
+  silicon initialization.
+
+  @param[in] FspsUpdDataPtr     Pointer to the FSPS_UPD data structure.
+                                If NULL, FSP will use the default parameters.
+
+  @retval EFI_SUCCESS                 FSP execution environment was initialized successfully.
+  @retval EFI_INVALID_PARAMETER       Input parameters are invalid.
+  @retval EFI_UNSUPPORTED             The FSP calling conditions were not met.
+  @retval EFI_DEVICE_ERROR            FSP initialization failed.
+  @retval FSP_STATUS_RESET_REQUIREDx  A reset is reuired. These status codes will not be returned during S3.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *FSP_SILICON_INIT) (
+  IN  VOID    *FspsUpdDataPtr
+  );
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspGlobalData.h b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspGlobalData.h
new file mode 100644
index 0000000000..687d4a86db
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspGlobalData.h
@@ -0,0 +1,68 @@
+/** @file
+
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  This file and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSP_GLOBAL_DATA_H_
+#define _FSP_GLOBAL_DATA_H_
+
+#include <FspEas.h>
+
+#pragma pack(1)
+
+typedef enum {
+  TempRamInitApiIndex,
+  FspInitApiIndex,
+  NotifyPhaseApiIndex,
+  FspMemoryInitApiIndex,
+  TempRamExitApiIndex,
+  FspSiliconInitApiIndex,
+  FspApiIndexMax
+} FSP_API_INDEX;
+
+typedef struct  {
+   VOID               *DataPtr;
+   UINT32             MicrocodeRegionBase;
+   UINT32             MicrocodeRegionSize;
+   UINT32             CodeRegionBase;
+   UINT32             CodeRegionSize;
+   UINT32             CarBase;
+   UINT32             CarSize;
+} FSP_PLAT_DATA;
+
+#define FSP_GLOBAL_DATA_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'D')
+#define FSP_PERFORMANCE_DATA_SIGNATURE  SIGNATURE_32 ('P', 'E', 'R', 'F')
+
+typedef struct  {
+   UINT32             Signature;
+   UINT8              Version;
+   UINT8              Reserved1[3];
+   UINT32             CoreStack;
+   UINT32             StatusCode;
+   UINT32             Reserved2[8];
+   FSP_PLAT_DATA      PlatformData;
+   FSP_INFO_HEADER    *FspInfoHeader;
+   VOID               *UpdDataPtr;
+   VOID               *TempRamInitUpdPtr;
+   VOID               *MemoryInitUpdPtr;
+   VOID               *SiliconInitUpdPtr;
+   UINT8              ApiIdx;
+   UINT8              Reserved3[31];
+   UINT32             PerfSig;
+   UINT16             PerfLen;
+   UINT16             Reserved4;
+   UINT32             PerfIdx;
+   UINT64             PerfData[32];
+} FSP_GLOBAL_DATA;
+
+#pragma pack()
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspMeasurePointId.h b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspMeasurePointId.h
new file mode 100644
index 0000000000..d6de4fbb18
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspMeasurePointId.h
@@ -0,0 +1,62 @@
+/** @file
+
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  This file and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSP_MEASURE_POINT_ID_H_
+#define _FSP_MEASURE_POINT_ID_H_
+
+//
+// 0xD0 - 0xEF are reserved for FSP common measure point
+//
+#define  FSP_PERF_ID_MRC_INIT_ENTRY               0xD0
+#define  FSP_PERF_ID_MRC_INIT_EXIT                (FSP_PERF_ID_MRC_INIT_ENTRY +  1)
+
+#define  FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY      0xD8
+#define  FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT       (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY +  1)
+
+#define  FSP_PERF_ID_PCH_INIT_ENTRY               0xDA
+#define  FSP_PERF_ID_PCH_INIT_EXIT                (FSP_PERF_ID_PCH_INIT_ENTRY +  1)
+
+#define  FSP_PERF_ID_CPU_INIT_ENTRY               0xE0
+#define  FSP_PERF_ID_CPU_INIT_EXIT                (FSP_PERF_ID_CPU_INIT_ENTRY +  1)
+
+#define  FSP_PERF_ID_GFX_INIT_ENTRY               0xE8
+#define  FSP_PERF_ID_GFX_INIT_EXIT                (FSP_PERF_ID_GFX_INIT_ENTRY +  1)
+
+#define  FSP_PERF_ID_ME_INIT_ENTRY                0xEA
+#define  FSP_PERF_ID_ME_INIT_EXIT                 (FSP_PERF_ID_ME_INIT_ENTRY +  1)
+
+//
+// 0xF0 - 0xFF are reserved for FSP API
+//
+#define  FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY           0xF0
+#define  FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT            (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)
+
+#define  FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY         0xF2
+#define  FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT          (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)
+
+#define  FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY           0xF4
+#define  FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT            (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)
+
+#define  FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY        0xF6
+#define  FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT         (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)
+
+#define  FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY         0xF8
+#define  FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT          (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)
+
+#define  FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY    0xFA
+#define  FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT     (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)
+
+#define  FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY  0xFC
+#define  FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT   (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1)
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspStatusCode.h b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspStatusCode.h
new file mode 100644
index 0000000000..1baaf71188
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/FspStatusCode.h
@@ -0,0 +1,46 @@
+/** @file
+  Intel FSP status code definition
+
+  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  This file and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _FSP_STATUS_CODE_H_
+#define _FSP_STATUS_CODE_H_
+
+//
+// FSP API - 4 BITS
+//
+#define FSP_STATUS_CODE_TEMP_RAM_INIT                0xF000
+#define FSP_STATUS_CODE_MEMORY_INIT                  0xD000
+#define FSP_STATUS_CODE_TEMP_RAM_EXIT                0xB000
+#define FSP_STATUS_CODE_SILICON_INIT                 0x9000
+#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION  0x6000
+#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION   0x4000
+#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000
+
+//
+// MODULE - 4 BITS
+//
+#define FSP_STATUS_CODE_GFX_PEIM                     0x0700
+#define FSP_STATUS_CODE_COMMON_CODE                  0x0800
+#define FSP_STATUS_CODE_SILICON_COMMON_CODE          0x0900
+#define FSP_STATUS_CODE_SYSTEM_AGENT                 0x0A00
+#define FSP_STATUS_CODE_PCH                          0x0B00
+#define FSP_STATUS_CODE_CPU                          0x0C00
+#define FSP_STATUS_CODE_MRC                          0x0D00
+#define FSP_STATUS_CODE_ME_BIOS                      0x0E00
+//
+// Individual Codes - 1 BYTE
+//
+#define FSP_STATUS_CODE_API_ENTRY                    0x0000
+#define FSP_STATUS_CODE_API_EXIT                     0x007F
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
new file mode 100644
index 0000000000..f43471dc88
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h
@@ -0,0 +1,204 @@
+/** @file
+  Intel FSP Header File definition from Intel Firmware Support Package External
+  Architecture Specification v2.0.
+
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  This file and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __FSP_HEADER_FILE_H__
+#define __FSP_HEADER_FILE_H__
+
+#define FSP_HEADER_REVISION_3   3
+
+#define FSPE_HEADER_REVISION_1  1
+#define FSPP_HEADER_REVISION_1  1
+
+///
+/// Fixed FSP header offset in the FSP image
+///
+#define FSP_INFO_HEADER_OFF    0x94
+
+#define OFFSET_IN_FSP_INFO_HEADER(x)  (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x
+
+#define FSP_INFO_HEADER_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'H')
+
+#pragma pack(1)
+
+///
+/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.
+///
+typedef struct {
+  ///
+  /// Byte 0x00: Signature ('FSPH') for the FSP Information Header.
+  ///
+  UINT32  Signature;
+  ///
+  /// Byte 0x04: Length of the FSP Information Header.
+  ///
+  UINT32  HeaderLength;
+  ///
+  /// Byte 0x08: Reserved.
+  ///
+  UINT8   Reserved1[2];
+  ///
+  /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.
+  ///
+  UINT8   SpecVersion;
+  ///
+  /// Byte 0x0B: Revision of the FSP Information Header.
+  ///
+  UINT8   HeaderRevision;
+  ///
+  /// Byte 0x0C: Revision of the FSP binary.
+  ///
+  UINT32  ImageRevision;
+  ///
+  /// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.
+  ///
+  CHAR8   ImageId[8];
+  ///
+  /// Byte 0x18: Size of the entire FSP binary.
+  ///
+  UINT32  ImageSize;
+  ///
+  /// Byte 0x1C: FSP binary preferred base address.
+  ///
+  UINT32  ImageBase;
+  ///
+  /// Byte 0x20: Attribute for the FSP binary.
+  ///
+  UINT16  ImageAttribute;
+  ///
+  /// Byte 0x22: Attributes of the FSP Component.
+  ///
+  UINT16  ComponentAttribute;
+  ///
+  /// Byte 0x24: Offset of the FSP configuration region.
+  ///
+  UINT32  CfgRegionOffset;
+  ///
+  /// Byte 0x28: Size of the FSP configuration region.
+  ///
+  UINT32  CfgRegionSize;
+  ///
+  /// Byte 0x2C: Reserved2.
+  ///
+  UINT32  Reserved2;
+  ///
+  /// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.
+  ///
+  UINT32  TempRamInitEntryOffset;
+  ///
+  /// Byte 0x34: Reserved3.
+  ///
+  UINT32  Reserved3;
+  ///
+  /// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.
+  ///
+  UINT32  NotifyPhaseEntryOffset;
+  ///
+  /// Byte 0x3C: The offset for the API to initialize the memory.
+  ///
+  UINT32  FspMemoryInitEntryOffset;
+  ///
+  /// Byte 0x40: The offset for the API to tear down temporary RAM.
+  ///
+  UINT32  TempRamExitEntryOffset;
+  ///
+  /// Byte 0x44: The offset for the API to initialize the CPU and chipset.
+  ///
+  UINT32  FspSiliconInitEntryOffset;
+} FSP_INFO_HEADER;
+
+///
+/// Signature of the FSP Extended Header
+///
+#define FSP_INFO_EXTENDED_HEADER_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'E')
+
+///
+/// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2.
+///
+typedef struct {
+  ///
+  /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.
+  ///
+  UINT32  Signature;
+  ///
+  /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.
+  ///
+  UINT32  Length;
+  ///
+  /// Byte 0x08: FSP producer defined revision of the table.
+  ///
+  UINT8   Revision;
+  ///
+  /// Byte 0x09: Reserved for future use.
+  ///
+  UINT8   Reserved;
+  ///
+  /// Byte 0x0A: FSP producer identification string
+  ///
+  CHAR8   FspProducerId[6];
+  ///
+  /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.
+  ///
+  UINT32  FspProducerRevision;
+  ///
+  /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.
+  ///
+  UINT32  FspProducerDataSize;
+  ///
+  /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.
+  ///
+} FSP_INFO_EXTENDED_HEADER;
+
+//
+// A generic table search algorithm for additional tables can be implemented with a
+// signature search algorithm until a terminator signature 'FSPP' is found.
+//
+#define FSP_FSPP_SIGNATURE  SIGNATURE_32 ('F', 'S', 'P', 'P')
+#define FSP_PATCH_TABLE_SIGNATURE  FSP_FSPP_SIGNATURE
+
+///
+/// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5.
+///
+typedef struct {
+  ///
+  /// Byte 0x00: FSP Patch Table Signature "FSPP".
+  ///
+  UINT32  Signature;
+  ///
+  /// Byte 0x04: Size including the PatchData.
+  ///
+  UINT16  HeaderLength;
+  ///
+  /// Byte 0x06: Revision is set to 0x01.
+  ///
+  UINT8   HeaderRevision;
+  ///
+  /// Byte 0x07: Reserved for future use.
+  ///
+  UINT8   Reserved;
+  ///
+  /// Byte 0x08: Number of entries to Patch.
+  ///
+  UINT32  PatchEntryNum;
+  ///
+  /// Byte 0x0C: Patch Data.
+  ///
+//UINT32  PatchData[];
+} FSP_PATCH_TABLE;
+
+#pragma pack()
+
+extern EFI_GUID gFspHeaderFileGuid;
+
+#endif
diff --git a/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h
new file mode 100644
index 0000000000..0713c6e019
--- /dev/null
+++ b/src/vendorcode/intel/edk2/UDK2015/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h
@@ -0,0 +1,23 @@
+/** @file
+  Intel FSP Hob Guid definition from Intel Firmware Support Package External
+  Architecture Specification v2.0.
+
+  Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+  This file and the accompanying materials are licensed and made available under
+  the terms and conditions of the BSD License.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THIS FILE IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __GUID_HOB_FSP_EAS_GUID__
+#define __GUID_HOB_FSP_EAS_GUID__
+
+extern EFI_GUID gFspBootLoaderTolumHobGuid;
+extern EFI_GUID gFspReservedMemoryResourceHobGuid;
+extern EFI_GUID gFspNonVolatileStorageHobGuid;
+
+#endif