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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-03-16 19:01:48 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-06-14 19:44:08 +0000
commit3dc1792f1df9a9cd982bb63d3b29cc16c08bd7f6 (patch)
treeca58c0c5d8ace4df40fa68adf9bf22c55b00a522 /src/vendorcode/google
parent5c124a97aaea675bdff1d690993e17bcbd901a2f (diff)
ChromeOS: Separate NVS from global GNVS
Allocate chromeos_acpi in CBMEM separately from GNVS. Change-Id: Ide55964ed53ea1d5b3c1c4e3ebd67286b7d568e4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/vendorcode/google')
-rw-r--r--src/vendorcode/google/chromeos/gnvs.c20
-rw-r--r--src/vendorcode/google/chromeos/gnvs.h13
2 files changed, 19 insertions, 14 deletions
diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c
index 9395f45fba..531463b273 100644
--- a/src/vendorcode/google/chromeos/gnvs.c
+++ b/src/vendorcode/google/chromeos/gnvs.c
@@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <acpi/acpi_gnvs.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
#include <types.h>
#include <string.h>
#include <stdlib.h>
@@ -16,7 +17,7 @@
#include "chromeos.h"
#include "gnvs.h"
-static chromeos_acpi_t *chromeos_acpi;
+static struct chromeos_acpi *chromeos_acpi;
static size_t chromeos_vpd_region(const char *region, uintptr_t *base)
{
@@ -30,12 +31,14 @@ static size_t chromeos_vpd_region(const char *region, uintptr_t *base)
return region_device_sz(&vpd);
}
-void chromeos_init_chromeos_acpi(chromeos_acpi_t *init)
+void chromeos_init_chromeos_acpi(void)
{
size_t vpd_size;
uintptr_t vpd_base = 0;
- chromeos_acpi = init;
+ chromeos_acpi = cbmem_add(CBMEM_ID_ACPI_CNVS, sizeof(struct chromeos_acpi));
+ if (!chromeos_acpi)
+ return;
vpd_size = chromeos_vpd_region("RO_VPD", &vpd_base);
if (vpd_size && vpd_base) {
@@ -90,3 +93,12 @@ void smbios_type0_bios_version(uintptr_t address)
/* Location of smbios_type0.bios_version() string filled with spaces. */
chromeos_acpi->vbt10 = address;
}
+
+void acpi_fill_cnvs(void)
+{
+ const struct opregion cnvs_op = OPREGION("CNVS", SYSTEMMEMORY, (uintptr_t)chromeos_acpi,
+ sizeof(*chromeos_acpi));
+ acpigen_write_scope("\\");
+ acpigen_write_opregion(&cnvs_op);
+ acpigen_pop_len();
+}
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h
index 8f8e259e8a..f6dcaeaece 100644
--- a/src/vendorcode/google/chromeos/gnvs.h
+++ b/src/vendorcode/google/chromeos/gnvs.h
@@ -8,16 +8,9 @@
#define ACTIVE_ECFW_RO 0
#define ACTIVE_ECFW_RW 1
-/*
- * chromeos_acpi_t portion of ACPI GNVS is assumed to live at
- * 0x100 - 0x1000.
- */
-#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
-
-/* device_nvs_t is assumed to live directly after chromeos_acpi_t. */
#define GNVS_DEVICE_NVS_OFFSET 0x1000
-typedef struct {
+struct chromeos_acpi {
/* ChromeOS specific */
u32 vbt0; // 00 boot reason
u32 vbt1; // 04 active main firmware
@@ -39,8 +32,8 @@ typedef struct {
u32 vpd_rw_base; // dce pointer to RW_VPD
u32 vpd_rw_size; // dd2 size of RW_VPD
u8 pad[298]; // dd6-eff
-} __packed chromeos_acpi_t;
+} __packed;
-void chromeos_init_chromeos_acpi(chromeos_acpi_t *init);
+void chromeos_init_chromeos_acpi(void);
#endif