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authorPeter Lemenkov <lemenkov@gmail.com>2018-10-19 16:57:27 +0200
committerStefan Reinauer <stefan.reinauer@coreboot.org>2018-10-23 06:15:43 +0000
commit5797b2eb05ec46d877a2ae6b5e0c517ae54a6fe8 (patch)
tree1b23efeb6e987f4886ffd5afa12418234eb988b4 /src/vendorcode/cavium/bdk
parent39315985e89e6ef3e7c01e697faf439280045157 (diff)
src: Typo fix (cosmetic)
Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/29196 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/vendorcode/cavium/bdk')
-rw-r--r--src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
index 192a8a9194..0fcc180da8 100644
--- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
+++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c
@@ -3295,7 +3295,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node,
mem_size_mbytes *= 2;
}
- /* Mask with 1 bits set for for each active rank, allowing 2 bits per dimm.
+ /* Mask with 1 bits set for each active rank, allowing 2 bits per dimm.
** This makes later calculations simpler, as a variety of CSRs use this layout.
** This init needs to be updated for dual configs (ie non-identical DIMMs).
** Bit 0 = dimm0, rank 0