From 5797b2eb05ec46d877a2ae6b5e0c517ae54a6fe8 Mon Sep 17 00:00:00 2001 From: Peter Lemenkov Date: Fri, 19 Oct 2018 16:57:27 +0200 Subject: src: Typo fix (cosmetic) Change-Id: I81985bd2836bdeb369587f170504a8a048ee496b Signed-off-by: Peter Lemenkov Reviewed-on: https://review.coreboot.org/29196 Reviewed-by: Stefan Reinauer Tested-by: build bot (Jenkins) --- src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/vendorcode/cavium/bdk') diff --git a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c index 192a8a9194..0fcc180da8 100644 --- a/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c +++ b/src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c @@ -3295,7 +3295,7 @@ int init_octeon3_ddr3_interface(bdk_node_t node, mem_size_mbytes *= 2; } - /* Mask with 1 bits set for for each active rank, allowing 2 bits per dimm. + /* Mask with 1 bits set for each active rank, allowing 2 bits per dimm. ** This makes later calculations simpler, as a variety of CSRs use this layout. ** This init needs to be updated for dual configs (ie non-identical DIMMs). ** Bit 0 = dimm0, rank 0 -- cgit v1.2.3